Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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In the Up Conversion process, the sck_sync, pfir filter, cic filter, and toutf_hold_sync will typically require
synchronization. The sck_sync is used to synchronize the divided clock. The fir_sync is used to synchronize the
PFIR. The coef_sync is used to synchronize switching between two banks of coefficients. The cic_sync and fir_sync
need to be selected to a common sync signal. The toutf_hold_sync is used to synchronize the decimation of the real
or parallel IQ data DUC output.
Table 5. Sync Modes
MODE SYNC SOURCE
0, 1 Off (never asserted)
2 SIA
3 SIB
4 one_shot
5 TC (terminal count (general timer)
6, 7 On (always active)
NOTE:
The internal syncs are active high. The SIA and SIB inputs
have been inverted to be the active high syncs SIA and SIB
internally.
The one_shot can either be a level or a pulse as described in Table 15. The level mode is used to initialize the chip;
the pulse mode is used to synchronously switch frequency, phase, or gain values.
The SIA input can then be used to initialize and flush the channels and the SIB sync input can be used, if desired,
to synchronize the phases of the NCOs.
The recommended sync mode settings are summarized in Table 6.
The SIA and SIB sync inputs are either connected to a user defined sync generator, for example, an FPGA, or are
tied to a GC5016 chip’s sync output pin (SO). If there are multiple GC5016 chips in the system, then the SO pin of
one chip can be used to drive the SIA input of all chips, and the SO pin of another chip can drive the SIB inputs of
all chips. This arrangement allows the user to use the SO sync output to synchronously drive the SIA or SIB sync
inputs of other GC5016s. The sync source for SO is selected using the soB_sync control bits in address 1.
Table 6. Recommended Sync Settings
Global Syncs (Address 1) Channel Syncs (Pages 0x14, 0x34, 0x54, and 0x74 Address
0x15)
Sync Value Description Sync Value Description
soB_sync 4 (OS) The SO output is used during
initialization
fir_sync 2 (SIA) Sync FIR during initialization
CIC and Mixer Syncs (Page 0x80 and 0xa0, Addresses 0x16 and
0x1E)
coef_sync 7 (always) For use with multiple coefficient
sets
Sync Value Description gain_sync 4 (OS) Sync gain when changing base
value. Manual Gain set to 6,7, for
DDC AGC set to initial sync
source. In DUC mode set to
always.
freq_sync 7 (always) Use frequency settings as they are
loaded
pwr_mtr_sync 2 (SIA) Synchronization starts a new
I^2+Q^2 accumulation cycle
phase_sync 7 (always) Use phase settings as they are
loaded
sck_sync 2 (SIA) Sync the serial clock during
initialization
dith_sync 0 (never) Can free run. Set to 7 (always) to
disable
nco_sync 3 (SIB) For NCO updates. Disrupts signal
processing when sync occurs.
flush_sync 0 (never) Set CIC integrator to 0, set to 0 for
DDC, and sync source for DUC
(shouldn’t be repetitive sync)
cic_sync 2 (SIA) Sync CIC during initialization