Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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Table 10. FirA Control RAMs
BLOCK PAGES DESCRIPTION
FirA 00−1F Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for A
FirB 20−3F Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for B
FirC 40−5F Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for C
FirD 60−7F Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for D
Table 11 lists the control registers for FirA.
Table 11. FirA Control Registers
PAGE ADDRESS REGISTER DESCRIPTION
0−F 10−1F FIR coefficients
10 10−1F Swap ram contents
11 10−1F BE ram contents
12 10 Coefficient address generator
12 11 Common address generator
12 12 Forward read address generator
12 13 Forward write address generator
12 14 Backward read address generator
12 15 Backward write address generator
12 16 Backward end cell read address generator
12 17 Backward end cell write address generator
12 18 Forward write strobe
12 19 Backward write strobe
12 1a Backward end cell read bypass
13 10 Transmit input formatter
13 11 Transmit frame strobe controls
13 12 Transmit frame counter
13 13 Gain 16 LSB’s
13 14 Gain controls
13 15 AGC minimum adaptation limit
13 16 AGC maximum adaptation limit
13 17 AGC counts and threshold
13 18 AGC loop gains
13 19 AGC gain read back
13 1a Power meter least significant 16 bits
13 1b Power meter most significant 16 bits
13 1c Power meter status
13 1d Power meter Integration time
13 1e Receive output formatter
13 1f Receive checksum
14 10 FIR swap ram controls
14 11 FIR accumulator controls
14 12 FIR output control
14 13 FIR sync count
14 14 FIR clock
14 15 Channel syncs