Specifications


SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
www.ti.com
69
17.5 Global Registers
The following tables describe the various bit fields contained in each of the global control registers.
Table 14. Global Register Reset and Clock Control Address 0x0 Bits 15.8 Set at Power Up
Rcv Tx FIELD BITS Dflt DESCRIPTION
− − ck_loss_status 1..0
D D en_ck_loss 8 1 Enable clock loss detection. Highly recommended.
C C pwr_dwn_fir_A 9 Power down PFIR in A. Power down puts the GC5016 section in reset and disables the clock.
It does not reset the control registers.
C C pwr_dwn_fir_B 10 Power down PFIR in B
C C pwr_dwn_fir_C 11 Power down PFIR in C
C C pwr_dwn_fir_D 12 Power down PFIR in D
C C pwr_dwn_cic_AB 13 Power down cic/mix for A and B
C C pwr_dwn_cic_CD 14 Power down cic/mix for C and D
C C master_reset 15 Power down all sections
Table 15. General Sync Global Address 0x1
RCV TX FIELD BITS Dflt DESCRIPTION
D D soB_sync 2..0 2 Signal selection for sync_out_B
− − one_shot 4..3 One shot control. (=0) Armed issue one shot when LSB goes high; (=1) issues one shot on
transition of LSB to high safe state to be left in; (=2) level output 0; (=3) level output 1
Table 16. Page and Revision Global Address 0x2
Rcv Tx FIELD BITS Dflt DESCRIPTION
− − page 7..0 Page register
− − chip_rev 15..8 Chip revision. Read only. Currently 1.
Table 17. Output Enables Global Address 0x3 Cleared at Power Up
Rcv Tx FIELD BITS Dflt DESCRIPTION
C C en_AO 0 Enable data output AO
C C en_AFS 1 Enable frame strobe and output clock for A
C C en_BO 2 Enable data output BO
C C en_BFS 3 Enable frame strobe and output clock for B
C C en_CO 4 Enable data output CO
C C en_CFS 5 Enable frame strobe and output clock for C
C C en_DO 6 Enable data output DO
C C en_DFS 7 Enable frame strobe and output clock for D
C C en_soB 8 Enable sync_out_B and iflag
D D ckp_A 9 0 Invert ACK
D D ckp_B 10 0 Invert BCK
D D ckp_C 11 0 Invert CCK
D D ckp_D 12 0 Invert DCK
X D sumin_clr 13 0 Force sumin port to zero