Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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17.6 FIR Control RAMs
The programmable filter has three RAM’s used to control its operation.
PAGE ADDRESS REGISTER DESCRIPTION
0−F 10−1F FIR coefficients
10 10−1F Swap ram address index
11 10−1F BE ram Bit Map
The filter coefficients are stored in a 16-word (by 16 bit) RAM, in each of 16 filter cells. The coefficients are 16-bit
two’s complement. The coefficients can be read without interrupting normal operation. Changing the coefficients
during normal operation can cause erroneous output should the hardware be reading a coefficient value
simultaneously. The coefficients can be divided into banks to allow safe updating and synchronous changing to a new
set. The coefficients are stored in addresses 0x10 to 0x1F on the FIR Control RAM pages:
0x0 to 0xF (for channel A),
0x20 to 0x2F (for channel B),
0x40 to 0x4F (for channel C),
0x60 to 0x6F (for channel D)
The configuration software takes the filter coefficients from a file and writes them to the appropriate RAM locations.
17.7 Swap RAMs
The Swap RAM can re-order the data for use by the forward delay line. The Swap RAM is divided into two halves.
The PFIR reads from the last stored set of data, and the input is written to the other half. The programmed portion
of the swap RAM, is the address of the new written data. A counter is used to read the address-pointer-value, and
write the newly received data at the pointed address.
Normally, this RAM is programmed so the content of each location equals its address (effectively bypassing it). In
the future, this RAM can be used to allow complex coefficients by allowing the same data to be read twice. The swap
RAM is on page 0x10 addresses 0x10 to 0x1F. Table 46 has additional Swap RAM controls for the write and read
address counters. The configuration software automatically writes this RAM. Currently there is no manual override
within the configuration software.
17.8 Backend RAM
The backend RAM encodes several fields into a 16 word by 16-bit RAM. The backend RAM is used to control the
16
th
FIR cell. There is a generic address that is programmed for all 16 cells. The 16
th
fir-cell functions may be different
from the other 15 cells, and may require different configuration. The bits are mapped as shown in Table 18.
The configuration software calculates the appropriate values for this RAM. There is no manual override option in the
configuration software.
Table 18. Backward End Cell Control RAM Bit Map
BITS DESCRIPTION
3..0 Backward end cell write address map for first iteration
7..4 Backward end cell write address map for second iteration
8 Backward end cell write enable
12..9 Backward end cell read address map
13 Blank feedback (end cell only) for odd symmetry first iteration
14 Blank feedback (end cell only) for odd symmetry second iteration
15 Unused