Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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Table 43. Power Meter Integration Time Page 0x13 Address 0x1D
Rcv Tx FIELD BITS Dflt DESCRIPTION
D D pwr_mtr_integ 15..0 0 Power meter integration time in words
17.13 DDC Receive Output Formatter Controls
The output modes TDM, interleavedIQ, parallel IQ, or embedded gain and IQ are controlled from table 44. Although
these are channel controls, the setup between channels must be correct for TDM mode, which is setup for all DDC
channels. The Transmit DUC diagnostic source is also in this table. Table 45 if the checksum value read in the
diagnostic test for a specific channel.
Table 44. Receive Output Formatter Page 0x13 Address 0x1E
Rcv Tx FIELD BITS Dflt DESCRIPTION
C X routf_pins 2..0 Receive output formatter active pins. Active pins are always the MSBs. Set to 1, 2, or 4 for 4,
8, or 16 active pins.
C X routf_bits 7..3 Receive output formatter bits in a word. Set to 1, 2, 4, 8, 16, or 32 to get a word size of 4, 8,
12, 16, or 20.
C X routf_iqmux 8 Receive output complex (1) or real (0) per port. Note that when splitiq is active, routf_iqmux
should be set to real.
C C routf_pwrdown 9 Power down receive output formatter block.
C X routf_ctdm 11 Activate TDM receive output.
D D pwr_test 12 0 Test mode for power meter. 0 for normal operation
D D tx_pat_gen 14..13 0 Transmit pattern generator enable and source selection off (0), random (1), constant 0x4000
(2), random with bit 14 inverted (3).
Table 45. Receive Checksum Page 0x13 Address 0x1F
Rcv Tx FIELD BITS Dflt DESCRIPTION
− − Rcv_checksum 15..0 − Checksum results for receive (read only).
17.14 Additional FIR Filter Controls
The Swap RAM controls are for the counters that write and read data from the FIR input to the Forward Delay Line.
This register is calculated through the cmd5016 software. The FIR Accumulator controls adds the partial sums from
the FIR cells, and controls the local FIR accumulator memory.
The FIR Output page, determines the FIR output format, provides scaling and rounding. The FIR Sync Count is used
to maintain the internal FIR cycle count. The FIR sync is used at the beginning of each new FIR cycle.
The FIR Clock Control is used to determine the number of active clocks within the FIR cycle count. Reducing the
FIR clocks within a cycle is used to lower the average Core power.
Table 46. FIR Swap Ram Controls Page 0x14 Address 0x10
Rcv Tx FIELD BITS Dflt DESCRIPTION
E E swap_wa_cnt 3..0 FIR swap write address down count
E E swap_ra_cnt 7..4 FIR swap read address down count
E E swap_xmt 8 FIR swap RAM in transmit (1) or receive (0)
E E swap_cmplx 9 FIR swap expects complex from CIC (1) or real (0)
E E fir_fb 10 FIR forward broadcast (1) or not (0)
E E swap_fb 11 FIR swap RAM in forward broadcast (1) or not (0)
E E swap_rcv_tdly 12 FIR swap RAM. Reduces cic to FIR data valid delay by 1 when cic is bypassed – helps with
data alignment in certain cases. Calculated by software.