Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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77
17.16 CIC and MIXER Control Registers
There are two cicmix blocks. The blocks are arranged as channel AB and channel CD:
page 0x80, addresses 0x10−0x17 channel A,
page 0x80, addresses 0x18 to 0x1F channel B,
page 0xA0, addresses 0x10−0x17 channel C,
page 0xA0, addresses 0x18 to 0x1F channel D.
Table 52 and 59 lists the CIC controls. The cic_shift, cic_rshift, cic_rcv_full, are the cic gain controls. The cic_rcv,
cic_xmt_5stg, cic_2x, cic_xmt_d6stg, and cic_bypass are the mode controls. The cic_rcv_cross is used to select
the DDC input for the dual CIC in channels B and D.
Table 53, 54, 55, and 56 set the frequency register (delta phase) and phase (initial phase) values.
Table 57 is the mixer configuration, this sets the I and Q data source, and the cosine and sine multiplier selections.
Table 58 is the mixer synchronization register.
Table 52. CIC Mode Page 0x80 Address 0x10
Rcv Tx FIELD BITS Dflt DESCRIPTION
C C cic_shift 5..0 CIC is followed by a shifter by a shifter to compensate for CIC gain. 0 ≤ cic_shift ≤ 39.
C C cic_rcv 7..6 CIC mode is quiet (0), receive (1), transmit (2), or illegal (3)
X C cic_xmt_5stg 8 CIC transmits five stages (1), rather than the normal six stages (0)
C X cic_rshift 9 Upshift 1 bit in receive mode after CIC filtering before rounding
C C cic_2x 10 Operate the CIC in double rate mode
X C cic_xmt_d6stg 11 Must be set for CIC in double rate and six stage, else clear
C X cic_rcv_cross 12 Use cross-strapped CIC inputs in receive. Set for splitiq mode
C X cic_rcv_full 13 Saturate CIC output at full scale (1) for nonsymmetrical FIR or half scale (0) for symmetric
FIR. Only affects receive outputs.
C C cic_bypass 14 Bypass CIC in transmit (1), must also set cic_shift (39) and ncic (0). Clear in receive.
− − cic_fl_status 15 CIC flush status sticky bit. Chip sets if autoflushed. User must clear.
Table 53. Phase Page 0x80 Address 0x11
Rcv Tx FIELD BITS Dflt DESCRIPTION
D D phase 15..0 0 Phase is phase/2
16
Hz
Table 54. Frequency (LSB) Page 0x80 Address 0x12
Rcv Tx FIELD BITS Dflt DESCRIPTION
D D freq_lsb 15..0 0 Bottom 16 bits of frequency
Table 55. Frequency (mid) Page 0x80 Address 0x13
Rcv Tx FIELD BITS Dflt DESCRIPTION
D D freq_mid 15..0 0 Middle 16 bits of frequency
Table 56. Frequency (MSB) Page 0x80 Address 0x14
Rcv Tx FIELD BITS Dflt DESCRIPTION
M M freq_msb 15..0 Top 16 bits of frequency. Values in Table 54 through Table 56 may be set using the pseudo
field freq.