Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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Table 57. Mixer Page 0x80 Address 0x15
Rcv Tx FIELD BITS Dflt DESCRIPTION
M X mix_rcv_sel 1..0 Mixer input selection in receive (paths a, b, c, or d for 0, 1, 2, or 3 respectively).
C X mix_rcv_cmplx 2 Set for receive complex input at full rate or double rate.
C C mix_inv_qsin 4 Invert the output of Qdata by sin in the mixer.
C C mix_qsin 6..5 Select data input to qsin multiplier as zero (0), receive (1), transmit cross-strapped (2), or
transmit (3). Transmit cross-strapped is for transmit in splitiq or double rate modes.
C C mix_inv_qcos 7 Invert the output of Qdata by cos in the mixer.
C C mix_qcos 9..8 Select data input to qcos multiplier as zero (0), receive (1), transmit cross-strapped (2), or
transmit (3). Transmit cross-strapped is for transmit in splitiq or double rate modes.
C C mix_inv_isin 10 Invert the output of Idata by sin in the mixer.
C C mix_isin 12..11 Select data input to isin multiplier as zero (0), receive (1), transmit cross-strapped (2), or
transmit (3). Transmit cross-strapped is for transmit in splitiq or double rate modes.
C C mix_inv_icos 13 Invert the output of Idata by cos in the mixer.
C C mix_icos 15..14 Select data input to icos multiplier as zero (0), receive (1), transmit cross-strapped (2), or
transmit (3). Transmit cross-strapped is for transmit in splitiq or double rate modes.
Table 58. NCO Syncs Page 0x80 Address 0x16
Rcv Tx FIELD BITS Dflt DESCRIPTION
D D freq_sync 2..0 6 Sync source for frequency word update
D D phase_sync 5..3 6 Sync source for phase word update
D D dith_sync 8..6 0 Sync source for dither update. Typically set to never. Set to always to disable.
D D nco_sync 11..9 0 Sync source for nco word update. Disrupts signal processing when sync occurs
D D flush_sync 14..12 0 Sync source for cic flush. Disrupts signal processing when sync occurs.
D D dith_test 15 0 Experimental dither mode, set to 0.
Table 59. CIC Count and Sync Page 0x80 Address 0x17
Rcv Tx FIELD BITS Dflt DESCRIPTION
C C ncic 11..0 CIC decimation / interpolation count minus one
D D cic_sync 14..12 2 Sync source for cic counter. suggested value matches the fir_sync setting
17.17 Transmit Sum Tree Registers
The Table 60 register variables select the sum tree logic selection. See Table 4, and figures 24 through 26.
Table 60. Sum Tree Sum Selection Page 0x81 Address 0x10
Rcv Tx FIELD BITS Dflt DESCRIPTION
X C sum_sell 7..0 Selects inputs for I sum both A and B paths.
X C sum_selQ 15..8 Selects inputs for Q sum both A and B paths.