Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
www.ti.com
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APPLICATION INFORMATION
19 BOARD BRING-UP PROCEDURE
This section describes a recommended procedure for checkout of a board using the GC5016. The various test files
are available on the website.
19.1 JTAG
The 1.8-Vdc VCore and 3.3-Vdc VPad should be within nominal values before using the JTAG or the Control Bus.
The TRST JTAG signal is a logic ’1’ for JTAG testing. The TRST JTAG signal is a logic ’0’ for nominal operation. The
TRST signal forces the JTAG Tap Controller to be in an idle state when the signal is logic ’0’.
If JTAG is not used, the TRST signal should be tied to GND.
19.1.1 Basic Control Path
Write reset value (0xFFFF) to register 0. Read back to see 0xFFF[C−F]. The bottom two bits are status bits and can
be any value. Write and read the page register (address 0x2). The lower byte should be just what you write in. The
upper byte should read back the revision (currently 1), regardless of what was written. If possible, use a scope to
capture the event so you can confirm setup/hold, output delay, strobe pulse width, voltage levels, and signal integrity.
19.1.2 Thorough Control Path Test
Use the control_check.gc101 script to read and write every control register and coefficient RAM in the chip with all
0’s, 1’s, 5’s and A’s and it then tests to see that the proper results are returned. Two commands are used (dwr16 and
dcm16) as shown in the following table:
dwr16 address data Write to the chip (both address and data are in hex)
dcm16 address mask expected_data Reads from the chip, masks the results, and checks against
the expected data.
The user software should accumulate errors as miscompared values. The control path test should have no errors.
The files are contained in the GC5016 Diagnostic Configuration File on the TI Web site at www.ti.com.
19.1.3 Built-in Self-test
These built-in self-tests provide the chip with input data using an internal pattern generator, an internal sync using
the general timer in the chip, and analyzes the output using a checksum generator. These tests depend on the board
to provide a solid control path, good clock, and good power. They generally work by setting the chip into a particular
mode, then running the patterns (typically for at least four million clocks), then reading out the checksum result. Four
checksum configurations are provided to provide good coverage of chip internals. If possible, use a scope to check
the quality of the clock, power, and ground. Table 72 provides the addresses to find the resultant checksums.
Table 72. Checksum Addresses
Transmit Receive
Channel A
Receive
Channel B
Receive
Channel C
Receive
Channel D
Page 0xA1 0x13 0x33 0x53 0x73
Address 0x15 0x1F 0x1F 0x1F 0x1F