Product data

TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 14 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
When at least one of the bits PRTL2, PRTL1, PRL2, PRL1 or PTL is high, then INT is low.
The bits having caused the interrupt are cleared when register HSR has been read-out.
The same occurs with INTAUXL, if not disabled.
In case of an emergency deactivation (by bits PRTL2, PRTL1, SUPL, PRL2, PRL1
or PTL), bit START (bit 0 in the PCR) is automatically reset by hardware.
At power-on, or after a supply voltage drop-out, bit SUPL is set and pin INT
= low. Pin INT
will return to high level at the end of the alarm pulse RSTOUT (see Figure 3
).
Bit SUPL will be reset only after a status register read-out outside the alarm pulse.
A minimum time of 2 µs is needed between two successive read operations of
register HSR, as well as between reading of register HSR and activation (write in
register PCR).
8.2.1.3 Time-out registers
The three Time-Out Registers (TOR1, TOR2 and TOR3) form a programmable 24-bit ETU
counter, or two independent counters (one 16-bit and one 8-bit). The value to load in
registers TOR1, TOR2 and TOR3 is the number of ETU to count. The time-out counters
may only be used when a card is active with a running clock.
[1] Register value at reset: all bits are cleared after reset.
[1] Register value at reset: all bits are cleared after reset.
Table 7. Description of HSR bits
Bit Symbol Description
7 HS7 not used
6PRTL2protection 2: Bit PRTL2 = 1 when a fault has been detected on card
reader 2. Bit PRTL 2 is the OR-function of the protection on pin V
CC2
and pin RST2.
5PRTL1protection 1:. Bit PRTL1 = 1 when a fault has been detected on card
reader 1. Bit PRTL 1 is the OR-function of the protection on pin V
CC1
and pin RST1.
4SUPL supervisor latch. Bit SUPL = 1 when the supervisor has been
activated.
3PRL2 presence latch 2: Bit PRL2 = 1 when a level change has occurred on
pin PRES2.
2PRL1 presence latch 1: Bit PRL1 = 1 when a level change has occurred on
pin PRES1.
1 INTAUXL auxiliary interrupt change: Bit INTAUXL = 1 if the level on
pin INTAUX has been changed.
0PTL overheating: Bit PTL = 1 if overheating has occurred.
Table 8. Register TOR1 (address 09H; write only)
[1]
7 6 5 4 3 2 1 0
TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0
Table 9. Register TOR2 (address 0AH; write only)
[1]
7 6 5 4 3 2 1 0
TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8