Product data

TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 17 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.2 ISO UART registers
8.2.2.1 UART Transmit Register (UTR)
[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to transmit a character to the selected card, it writes the
data in direct convention in the UART transmit register. The transmission:
• Starts at the end of writing (on the rising edge of signal WR\) if the previous character
has been transmitted and if the extra guard time has expired
• Starts at the end of the extra guard time if this one has not expired
• Does not start if the transmission of the previous character is not completed
• With a synchronous card (bit SAN within register UCR2 is set), only signal D0 is
relevant and is copied on pin I/O of the selected card.
8.2.2.2 UART Receive Register (URR)
[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to read data from the card, it reads it from the UART
Receive Register (URR) in direct convention:
• With a synchronous card, only D0 is relevant and is a copy of the state of the selected
card I/O
• When needed, this register may be tied to a FIFO whose length ‘n’ is programmable
between 1 and 8; if n >1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
• With a parity error:
a. _ In protocol T = 0; the received byte is not stored in the FIFO and the error
counter is incremented. The error counter is programmable between 1 and 8.
When the programmed number is reached, then the bit PE is set in the status
register USR and INT0 falls low. The error counter must be reprogrammed to the
desired value after its count has been reached
b. _In protocol T = 1; the character is loaded in the FIFO and the bit PE is set
whatever the programmed value in the parity error counter
• When the FIFO is full, then the bit RBF in the status register USR is set. This bit is
reset when at least one character has been read from URR
• When the FIFO is empty, then the bit FE is set in the status register USR as long as
no character has been received.
Table 13. Register UTR (address 0DH; write only)
[1]
7 6 5 4 3 2 1 0
UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0
Table 14. Register URR (address 0DH; read only)
[1]
7 6 5 4 3 2 1 0
UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0