Product data

TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 18 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.2.3 Mixed Status Register (MSR)
The MSR relates the status of pin INTAUX, the cards presence contacts PRES1
and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive
ready indicator TBE/RBF. It also gives useful indications when switching the clock to or
from 1/2 f
int
and when driving the TDA8007BHL/C4 with fast controllers.
No bits within register MSR act upon signal INT
.
[1] Register value at reset: bits TBE/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set
after reset.
Table 15. Register MSR (address 0Ch; read only)
[1]
7 6 5 4 3 2 1 0
CLKSW FE BGT CRED PR2 PR1 INTAUX TBE/RBF
Table 16. Description of MSR bits
Bit Symbol Description
7 CLKSW clock switch: Bit CLKSW is set when the TDA8007BHL/C4 has
performed a required clock switch from
1
⁄
n
f
XTAL
to ⁄
2
f
int
, and is reset
when the TDA8007BHL/C4 has performed a required clock switch from
1
⁄
2
f
int
to
1
⁄
n
f
XTAL
. The application must wait until this bit is set or reset
before sending a new command to the card. This bit is reset at
power-on.
6FE FIFO Empty: Bit FE is set when the reception FIFO is empty. It is reset
when at least one character has been loaded in the FIFO.
5BGT block guard time: In protocol T = 1, bit BGT is linked with a 22-ETU
counter which is started at every START bit on pin I/O. Bit BGT is set if
the count is finished before the next START bit. This helps to verify that
the card has not answered before 22 ETU after the last transmitted
character, or that the reader is not transmitting a character before
22 ETU after the last received character.
In protocol T = 0, bit BGT is linked with a 16-ETU counter which is
started at every START bit on pin I/O. Bit BGT is set if the count is
finished before the next START bit. This helps to verify that the reader
is not transmitting a character before 16 ETU after the last received
character.
4 CRED control ready: It is advised bit CRED is used for driving the
TDA8007BHL/C4 with high speed controllers. Before writing in
registers TOC or UTR, or reading from register URR, check if bit CRED
is set. If reset, it means that the writing or reading operation will not be
correct because the controller is acting faster than the required time for
this operation:
3PR2 card 2 present: Bit PR2 = 1 when card 2 is present.