Product data

TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 22 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.2.4 FIFO Control Registers (FSR)
The FCR relates the parity error count and the FIFO length.
[1] Register value at reset: all relevant bits are cleared after reset.
8.2.2.5 UART Status Register (USR)
The USR is used by the microcontroller to monitor the activity of the ISO UART and that of
the time-out counter. If any of the status bits FER, OVR, PE, EA, TO1, TO2 or TO3 are
set, then signal INT
= low. The bit having caused the interrupt is reset 2 ms after the rising
edge of signal RD
during a read operation of register USR.
If bit TBE/RBF is set and if the mask bit DISTBE/RBF within register UCR2 is not set, then
also signal INT
= low. Bit TBE/RBF is reset 3 clock cycles after data has been written in
register UTR, or 3 clock cycles after data has been read from register URR, or when
changing from transmission mode to reception mode.
In order to avoid counting these clock cycles, bit CRED (described in register MSR) may
be used.
Table 17. Register FCR (address 0Ch; write only)
[1]
7 6 5 4 3 2 1 0
FC7 PEC2 PEC1 PEC0 FC3 FL2 FL1 FL0
Table 18. Description of FCR bits
Bit Symbol Description
7 FC7 not used
6
5
4
PEC2
PEC1
PEC0
Parity Error Count
PEC2, PEC1 and PEC0 determine the number of allowed repetitions
reception
The value 000 indicates that, if only one parity error has occurred,
bit PE is set; the value 111 indicates that bit PE will be set after 8 parity
errors.
In protocol T = 0:
If a correct character is received before the programmed error number
is reached, the error counter will be reset
- If the programmed number of allowed parity errors is reached, bit PE
in register USR will be set as long as register USR has not been read
- If a transmitted character has been NAK by the card, then the
TDA8007BHL/C4 will automatically re-transmit it a number of times
equal to the value programmed in bits PEC2, PEC1 and PEC0; the
character will be resent at 15 ETU
In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then
the automatic re-transmission is invalidated; the character manually
rewritten in register UTR will start at 13.5 ETU.
3 FC3 not used
2FL2 FIFO length. Bits FL2, FL1 and FL0 determine the depth of the FIFO:
1FL1
• 000=length1
• 111 = length 8.
0FL0