Product data

TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 23 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
If LCT mode is used for transmitting the last character, then bit TBE is not set at the end of
the transmission.
[1] Register value at reset: all relevant bits are cleared after reset.
Table 19. Register USR (address 0Eh; read only)
[1]
7 6 5 4 3 2 1 0
TO3 TO2 TO1 EA PE OVR FER TBE/RBF
Table 20. Description of USR bits
Bit Symbol Description
7TO3 Time-Out counter 3. Bit TO3 is set when counter 3 has reached its
terminal count.
6TO2 Time-Out counter 2. Bit TO2 is set when counter 2 has reached its
terminal count.
5TO1 Time-Out counter 1. Bit TO1 is set when counter 1 has reached its
terminal count.
4EA Early answer is high if the first START bit on the I/O during ATR has
been detected between the first 200 and 368 clock pulses with RST low
(all activities on the I/O during the first 200 clock pulses with RST low
are not taken into account) and before the first 368 clock pulses with
RST high. These two features are re-initialized at each toggling of RST
3PE Parity Error (PE). In protocol T = 0, bit PE = 1 if the UART has
detected a number of received characters with parity errors equal to the
number written in bits PEC2, PEC1 and PEC0 or if a transmitted
character has been NAK by the card a number of times equal to the
value programmed in bits PEC2, PEC1 and PEC0. It is set at 10.5 ETU
in the reception mode and at 11.5 ETU in the transmission mode.
In protocol T = 0, a character received with a parity error is not stored in
register FIFO (the card should repeat this character). In protocol T = 1,
a character with a parity error is stored in the FIFO and the parity error
counter is not active.
2OVR Overrun (OVR). Bit OVR = 1 if the UART has received a new character
whilst register FIFO was full. In this case, at least one character has
been lost.
1FER Framing Error (FER). Bit FER = 1 when pin I/O was not in the high
impedance state at 10.25 ETU after a START bit. It is reset when
register USR has been read-out.
0TBE/RBFTransmission Buffer Empty (TBE)/Reception Buffer Full (RBF).
Bits TBE and RBF share the same bit within register USR: when in
transmission mode the relevant bit is TBE; when in reception mode it is
RBF.
Bit TBE = 1 when the UART is in transmission mode and when the
microcontroller may write the next character to transmit in register UTR.
It is reset when the microcontroller has written data in the transmit
register or when bit T/R within register UCR1 has been reset either
automatically or by software. After detection of a parity error in
transmission, it is necessary to wait 13.5 ETU before rewriting the
character which has been NAK by the card. (Manual mode, see
Table 18 )
Bit RBF = 1 when register FIFO is full. The microcontroller may read
some of the characters in register URR, which clears bit RBF.