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Product data sheet Rev. 9.1 — 18 June 2012 27 of 51

NXP Semiconductors

TDA8007BHL

Multiprotocol IC card interface

8.2.3.5 Clock Configuration Registers (CCR)

The clock configuration registers CCR1, CCR2 and CCR3 relate the clock signals:

• For cards 1 and 2, register CCRx defines the clock for the selected card

• For cards 1, 2 and 3, register CCRx defines the clock to the ISO UART. It should be

noted that, if bit CKU in the prescaler register of the selected card (register UCR2) is

set, then the ISO UART is clocked at twice the frequency of the card, which allows

baud rates not foreseen in ISO 7816 norm to be reached.

[1] Register value at reset: all bits are cleared after reset.

Table 27. Description of UCRx1 bits

Bit Symbol Description

7 UC17 not used

6FIP Force Inverse Parity (FIP). If bit FIP is set to logic 1, the UART will

NAK a correctly received character, and will transmit characters with

wrong parity bits.

5FC Test. Bit FC is a test bit, and must be left at logic 0.

4PROTProtocol (PROT). Bit PROT is set if the protocol is T = 1

(asynchronous) and bit PROT = 0 if the protocol is T = 0.

3T/R Transmit/Receive (T/R). Bit T/R is set by software for transmission

mode. A change from logic 0 to 1 will set bit TBE in register USR.

Bit T/R is automatically reset by hardware if bit LCT has been used

before transmitting the last character.

2LCT Last Character to Transmit (LCT). Bit LCT is set by software before

writing the last character to be transmitted in the UTR. It allows

automatic change to reception mode. It is reset by hardware at the end

of a successful transmission. When LCT is being reset, the bit T/R is

also reset and the ISO 7816 UART is ready for receiving a character.

1SS Software convention Setting (SS). Bit SS is set by software before

ATR for automatic convention detection and early answer detection. It

is automatically reset by hardware at 10.5 ETU after reception of the

initial character.

0CONVConvention (CONV). Bit CONV is set if the convention is direct.

Bit CONV is either automatically written by hardware according to the

convention detected during ATR, or by software if the bit AUTOCONV

in register UCR2X is set.

Table 28. Register CCR1, CCR2 and CCR3 (address 01H; read and write)

[1]

7 6 5 4 3 2 1 0

CC7 CC6 SHL GST SC AC2 AC1 AC0

Table 29. Description of CCRx bits

Bit Symbol Description

7 CC7 not used

6 CC6 not used

5SHL Stop High or Low (SHL). If bit CST = 1, then the clock is

stopped at low level if bit SHL = 0, and at high level if

bit SHL = 1.