Product data
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 28 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
Clock switching constraints:
• f
int
is the frequency delivered by the internal oscillator
• In case of f
CLK
=f
XTAL
, the duty cycle must be ensured by the incoming clock signal on
pin XTAL1
• When switching from
1
⁄
n
f
XTAL
to
1
⁄
2
f
XTAL
or vice verse, only bit AC2 must be changed
(bits AC1 and AC0 must remain the same). When switching from
1
⁄
n
f
XTAL
to
1
⁄
2
f
XTAL
to
clock stopped or vice verse, only bits CST and SHL must be changed
• When switching from
1
⁄
n
f
XTAL
to
1
⁄
2
f
XTAL
or vice verse, a delay can occur between the
command and the effective frequency change on CLK (the fastest switching time is
from
1
⁄
2
f
XTAL
to
1
⁄
2
f
int
or vice verse, the best for duty cycle is from
1
⁄
8
f
XTAL
to
1
⁄
2
f
int
or
vice verse)
• It is necessary to survey the bit CLKSW in register MSR before re-transmitting
commands to the card.
8.2.3.6 Power Control Registers (PCR)
The power control registers PCR1 and PCR2:
• Start or stop card sessions
• Read from or write to auxiliary card contacts C4 and C8
• Are available only for cards 1 or 2.
To deactivate the card, only bit START should be reset.
[1] Register value at reset: all bits are cleared after reset.
4CST Clock Stop (CST). In the case of an asynchronous card,
bit CST defines whether the clock to the card is stopped or not; if
bit CST is reset, then the clock is determined by bits AC0, AC1
and AC2.
3SC Synchronous Clock (SC). In the event of a synchronous card,
then contact CLK is the copy of the value of bit SC; in reception
mode, the data from the card is available to bit UR0 after a read
operation of register URR; in transmission mode, the data is
written on the I/O line of the card when register UTR has been
written to and remains unchanged when another card is
selected.
2to0 AC Alternating Clock (AC). All frequency changes are
synchronous, thus ensuring that no spikes or unwanted pulse
widths occur during changes.
000 = f
XTAL
001 =
1
⁄
2
f
XTAL
010 =
1
⁄
4
f
XTAL
011 =
1
⁄
8
f
XTAL
100 to 111 =
1
⁄
2
f
int
Table 29. Description of CCRx bits …continued
Bit Symbol Description
Table 30. Register PCR1 and PCR2 (address 07H; read and write)
[1]
7 6 5 4 3 2 1 0
PCR7 PCR6 C8 C4 1V8 RSTIN 3V/5V START