Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 3 Operating Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
PLS63-W Hardware Interface Overview
2.1 Application Interface
31
Page 19 of 48
Table 4 lists the available I
2
S interface signals
2.1.7 Control Signals
2.1.7.1 Status LED
The GPIO5 interface line can be configured to drive a status LED that indicates different oper-
ating mode (for GPIOs see 2.1.5). GPIO and LED functionality are mutually exclusive.
To take advantage of this function connect an LED to the GPIO5/STATUS line as shown in
Figure 9
Figure 9: Status signaling with LED driver
Table 4: Overview of I
2
S pin functions
Signal name on
SMT application
interface
Signal configura-
tion inactive
Signal direction
Master
Description
DOUT PD O I
2
S data from PLS63-W to external
codec
DIN PD I I
2
S data from external codec to
PLS63-W
FSC PD O Frame synchronization signal to/
from external codec Word align-
ment (WS)
BCLK PU O Bit clock to external codec.
BCLK signal low/high time varies
between 45% and 55% of its clock
period.
VCC
STATUS
LED
GNDGND
R1
R2
R3