User Manual
Table Of Contents
- “Trilogy 3” MPCI
- Introduction
- Trilogy 3 Product Overview
- Document Purpose
- Key Features
- What’s Not Supported
- References
- WLAN System Architecture
- WLAN Block Diagram
- WLAN Component Descriptions
- WLAN Transmitter Path
- WLAN Receive Path
- WLAN Microprocessor Control
- WLAN Frequency Generation
- WLAN Hardware Environment
- WLAN Power Requirements
- Modem System Architecture
- Modem Block Diagram
- Modem Hardware Environment
- Modem Power Requirements
- Environmental Performance
- Regulatory
- Ethernet Software Driver and Feature Set
- Modem Software Driver and Feature Set
- Operating System Software Support
- AC’97 Modem Driver Package File Description
- SETUP Usage
- SETUP Customization
- Multilanguage Support
- LTHOMOL.exe (Homologation support utility)
- LTSMMSG.exe (User messaging & system audio support utility)
- Selection of Un-homologated Country Messaging
- Over Current Protection (OCP) Messaging
- System Audio Support
- Quality
Trilogy 3 MPCI
M3AWEB/56GA
Product Specification
Modem System Architecture
The 56K soft modem design is based on the Agere CSP1037 Scorpio chip set. This
chip set includes an integrated direct access arrangement (DAA) that provides a
programmable line interface to meet international telephone line requirements.
Unlike Controller or Controller-less modems, the AC’97 soft modem uses host CPU
computing power to process the incoming/outgoing data instead of having a dedicated
DSP local to the modem.
Isolation Barrier
Host Side Line Side Hook- Tip
Mini PCI AC’97 Device Device Switch
Host I/F Signals and Ring
SCP-16T CSP1037 DC
-16T Term.
Modem Block Diagram
Host Side (SCP-16T) has the AC’97 link protocol built-in for communication to the Host.
It is responsible to process data coming in and going out to the Line Side chip as well as
commands to control the Line Side for on-hook, off-hook, dial, ring detect. The host side
can be configured via Host Interface strapping pins as an AC’97 Primary (ID 00) or
Secondary (ID’s 01 or 10) Codec. For the (default) Primary mode, an on-board
24.576MHz oscillator is provided which is converted to the required internal and external
clock frequencies by a PLL within the Host Side chip. An analog Call-Progress signal is
provided at one of two Host Interface pins. Power for the digital portion of the Host Side
is provided by the host system’s 3.3VAUX supply. Power for the analog portion is
provided by a charge pump, which is driven by the data-stream of the isolation barrier.
The Scorpio chip set achieves an isolation barrier through low-cost, high-voltage
capacitors in conjunction with Agere’s proprietary signal processing techniques. These
techniques eliminate any signal degradation due to capacitor mismatches, common-
mode interference, or noise coupling. All transmit, receive, control, and ring detect data
are communicated through this barrier.
Line Side (CSP1037-16T) communicates data with the Host Side across the capacitive
barrier. The Line Side chip performs D/A and A/D conversion, provides the DAA
functions such as AC and DC impedance control, ring detection, and loop current
monitoring. This chip also controls the analog input/output to Tip/Ring via discrete
components. Power for the Line Side is derived from the telephone line.
The hook-switch and DC termination circuits of the DAA are implemented with discrete
transistors and passive components, controlled by the Line Side chip.
Intel Confidential – Controlled Access
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