Specifications

5102ch04.fm Draft Document for Review May 12, 2014 12:46 pm
140 IBM Power System S822 Technical Overview and Introduction
– to prevent outages the L4 Cache has the capability to perform a bank delete so that
faulty portions of the DRAM can be removed from the use
4.5.1 POWER7+ RAS features
Besides the improvements in the POWER8 Systems this section lists the existing POWER7+
RAS features that are in common with the new POWER8:
򐂰 Power-On Reset Engine (PORE)
Enables a processor to be re-initialized while the system remains running. This feature will
allow for the concurrent firmware updates situation, in which a processor initialization
register value needs to be changed. Concurrent firmware updates might be more
prevalent.
򐂰 L3 cache dynamic column repair
This self-healing capability completes cache-line delete and uses the PORE feature to
potentially avoid some repair actions or outages that are related to L3 cache.
򐂰 Accelerator RAS
New accelerators are designed with RAS features to avoid system outages in the vast
majority of faults that can be detected by the accelerators.
򐂰 Fabric Bus Dynamic Lane Repair
POWER7+ has spare bit lanes that can dynamically be repaired (using PORE). This
feature avoids any repair action or outage related to a single bit failure for the fabric bus.
4.6 Power-On Reset Engine
The POWER7+ chip includes a Power-On Reset Engine (PORE), a programmable hardware
sequencer responsible for restoring the state of a powered down processor core and L2
cache (deep sleep mode), or chiplet (winkle mode). When a processor core wakes up from
sleep or winkle, the PORE fetches code created by the POWER Hypervisor from a special
location in memory containing the instructions and data necessary to restore the processor
core to a functional state. This memory image includes all the necessary boot and runtime
configuration data that were applied to this processor core since power-on, including circuit
calibration and cache repair registers that are unique to each processor core. Effectively the
PORE performs a mini initial program load (IPL) of the processor core or chiplet, completing
the sequence of operations necessary to restart instruction execution, such as removing
electrical and logical fences and re initializing the Digital PLL clock source.
Because of its special ability to perform clocks-off and clocks-on sequencing of the hardware,
the PORE can also be used for RAS purposes:
򐂰 The service processor can use the PORE to concurrently apply an initialization update to
a processor core/chiplet by loading new initialization values into memory and then forcing
it to go in and out of winkle mode. This step happens, all without causing disruption to the
workloads or operating system (all occurring in a few milliseconds).
򐂰 In the same fashion, PORE can initiate an L3 cache dynamic “bit-line” repair operation if
the POWER Hypervisor detects too many recoverable errors in the cache.
򐂰 The PORE can be used to dynamically repair node-to-node fabric bit lanes in a POWER7+
processor-based server by quickly suspending chip-chip traffic during run time,
reconfiguring the interface to use a spare bit lane, then resuming traffic, all without causing
disruption to the operation of the server.