Specifications

Chapter 2. Architecture and technical overview 25

Draft Document for Review May 12, 2014 12:46 pm 5102ch02.fm

2.1.1 POWER8 processor overview

The POWER8 processor is manufactured using the IBM 22 nm Silicon-On-Insulator (SOI)

technology. Each chip is 649 mm

and contains 4.2 billion transistors. As shown in Figure 2-3,

the chip contains twelve cores, two memory controllers, PCIe Gen3 I/O controllers and an

interconnection system that connects all components within the chip. Each core has 512 KB

of L2 cache, and all cores share 96 MB of L3 embedded DRAM (eDRAM). The interconnect

also extends through module and board technology to other POWER8 processors in addition

to DDR3 memory and various I/O devices.

POWER8 systems utilize memory buffer chips to interface between the POWER8 processor

and DDR3 or DDR4 memory

. Each buffer chip also includes an L4 cache to reduce the

latency of local memory accesses.

Figure 2-3 The POWER8 processor chip

The POWER8 processor is designed for system offerings from single-socket servers to

multi-socket Enterprise servers. It incorporates a triple-scope broadcast coherence protocol

over local and global SMP links to provide superior scaling attributes. Multiple-scope

coherence protocols reduce the amount of SMP link bandwidth that is required by attempting

operations on a limited scope (single chip or multi-chip group) when possible. If the operation

cannot complete coherently, the operation is re-issued using a larger scope to complete the

operation.

Additional features that can augment performance of the POWER8 processor are:

򐂰 Support for DDR3 and DDR4 memory through memory buffer chips that offload the

memory support from the POWER8 memory controller

At the time of the publication, the available POWER8 processor-based systems use DDR3 memory.

Mem. Ctrl. L3 Cache & Chip Interconnect

8M L3

Region

Mem. Ctrl.

Local SMP Links

Accelerators

Local SMP Links

Accelerators

Core