Specifications

5102ch02.fm Draft Document for Review May 12, 2014 12:46 pm
26 IBM Power System S822 Technical Overview and Introduction
򐂰 L4 cache within the memory buffer chip that reduces the memory latency for local access
to memory behind the buffer chip; the operation of the L4 cache is transparent to
applications running on the POWER8 processor. Up to 128 MB of L4 cache can be
available for each POWER8 processor.
򐂰 Hardware transactional memory
򐂰 On-chip accelerators, including on-chip encryption, compression, and random number
generation accelerators
򐂰 Coherent Accelerator Processor Interface, which allow accelerators plugged into a PCIe
slot to access the processor bus using a low latency, high speed protocol interface.
򐂰 Adaptive power management
As in with the POWER7 processor, the POWER8 processor has a distributed Recovery Unit
(RU) that is responsible for saving each processor state and providing a checkpoint for
recovery should an error occur.
There are two versions of the POWER8 processor chip. Both chips use the same building
blocks. The scale-out systems use a 6-core version of POWER8. The 6-core chip is installed
in pairs in a Dual Chip Module (DCM) that plugs into a socket in the planar of the systems.
Functionally, it works as a single chip.
Figure 2-4 shows a graphic representation of the 6-core processor.
Figure 2-4 6-core POWER8 processor chip