Specifications

Chapter 2. Architecture and technical overview 27
Draft Document for Review May 12, 2014 12:46 pm 5102ch02.fm
Table 2-1 summarizes the technology characteristics of the POWER8 processor.
Table 2-1 Summary of POWER8 processor technology
2.1.2 POWER8 processor core
The POWER8 processor core is a 64-bit implementation of the IBM Power Instruction Set
Architecture (ISA) Version 2.07 and has the following features:
򐂰 Multi-threaded design, capable of up to eight-way simultaneous multithreading (SMT)
򐂰 32 KB, eight-way set-associative L1 instruction cache
򐂰 64 KB, eight-way set-associative L1 data cache
򐂰 Enhanced prefetch, with instruction speculation awareness and data prefetch depth
awareness
򐂰 Enhanced branch prediction, using both local and global prediction tables with a selector
table to choose the best predictor
򐂰 Improved out-of-order execution
򐂰 Two symmetric fixed-point execution units
򐂰 Two symmetric load/store units and two load units, all four of which can also run simple
fixed-point instructions
򐂰 An integrated, multi-pipeline vector-scalar floating point unit for running both scalar and
SIMD-type instructions, including the Vector Multimedia eXtension (VMX) instruction set
and the improved Vector Scalar eXtension (VSX) instruction set, and capable of up to
eight floating point operations per cycle (four double precision or eight single precision)
򐂰 In-core Advanced Encryption Standard (AES) encryption capability
򐂰 Hardware data prefetching with 16 independent data streams and software control
򐂰 Hardware decimal floating point (DFP) capability.
More information about Power ISA Version 2.07 can be found at:
https://www.power.org/documentation/power-isa-version-2-07/
Technology POWER8 processor
Die size 649 mm
2
Fabrication technology 򐂰 22 nm lithography
򐂰 Copper interconnect
򐂰 Silicon-on-Insulator
򐂰 eDRAM
Maximum processor cores 6 or 12
Maximum execution threads core/chip 8/96
Maximum L2 cache core/chip 512 KB/6 MB
Maximum On-chip L3 cache core/chip 8 MB/96 MB
Maximum L4 cache per chip 128 MB
Maximum memory controllers 2
SMP design-point 16 sockets with IBM POWER8 processors
Compatibility With prior generation of POWER processor