Specifications

Chapter 2. Architecture and technical overview 29
Draft Document for Review May 12, 2014 12:46 pm 5102ch02.fm
2.1.4 Memory access
On the Power S822, each POWER8 module has two memory controllers, each connected to
four memory channels. Each memory channel operates at 1600 MHz and connects to a
DIMM. Each DIMM on a POWER8 system has a memory buffer that is responsible for many
functions that were previously on the memory controller, such as scheduling logic and energy
management. The memory buffer also has 16 MB of L4 cache.
At the time of writing each memory channel can address up to 64 GB. Therefore the
Power S822 is capable of addressing up to 1 TB of total memory.
Figure 2-6 gives a simple overview of the POWER8 processor memory access structure in
the Power S822 server.
Figure 2-6 Overview of POWER8 memory access structure
2.1.5 On-chip L3 cache innovation and Intelligent Cache
Similar to POWER7 and POWER7+, the POWER8 processor utilizes a breakthrough in
material engineering and microprocessor fabrication to implement the L3 cache in eDRAM
and place it on the processor die. L3 cache is critical to a balanced design, as is the ability to
provide good signaling between the L3 cache and other elements of the hierarchy, such as
the L2 cache or SMP interconnect.
The on-chip L3 cache is organized into separate areas with differing latency characteristics.
Each processor core is associated with a fast 8 MB local region of L3 cache (FLR-L3) but also
has access to other L3 cache regions as shared L3 cache. Additionally, each core can
negotiate to use the FLR-L3 cache associated with another core, depending on reference
patterns. Data can also be cloned to be stored in more than one core’s FLR-L3 cache, again
depending on reference patterns. This
Intelligent Cache management enables the POWER8
processor to optimize the access to L3 cache lines and minimize overall cache latencies.
Figure 2-3 on page 25 and Figure 2-4 on page 26 show the on-chip L3 cache, and highlight
one fast 8 MB L3 region closest to a processor core.
POWER8
Module
Memo ry
Buffer
DRAM
Chips