Specifications

5102ch02.fm Draft Document for Review May 12, 2014 12:46 pm
34 IBM Power System S822 Technical Overview and Introduction
For more details, see chapter 2.11, “Energy management” on page 70.
2.1.10 Comparison of the POWER8, POWER7+ and POWER7 processors
Table 2-3 on page 31 shows comparable characteristics between the generations of
POWER8, POWER7+, and POWER7 processors.
Comparison of technology for the POWER8 processor and the prior generations
2.2 Memory subsystem
The IBM Power S822 is a two socket system that supports up to two POWER8 processor
modules. The server supports a maximum of 16 DDR3 CDIMM slots, with 8 DIMM slots per
installed processor. Memory features supported are 16 GB, 32 GB, an 64 GB and run at
speeds of 1600 MHz, allowing for a maximum system memory of 1024 GB.
These servers support an optional feature called Active Memory Expansion (#4793) that
allows the effective maximum memory capacity to be much larger than the true physical
memory. This feature executes innovative compression and decompression of memory
content by using a dedicated coprocessor to provide memory expansion up to 125%,
depending on the workload type and its memory utilization. As an example, a server with
256 GB RAM physically installed can effectively be expanded over 512 GB RAM. This
approach can enhance virtualization and server consolidation by allowing a partition to do
significantly more work with the same physical amount of memory or a server to run more
partitions and do more work with the same physical amount of memory.
Characteristics POWER8 POWER7+ POWER7
Technology 22 nm 32 nm 45 nm
Die size 649 mm
2
567 mm
2
567 mm
2
Number of transistors 4.2 billion 2.1 billion 1.2 billion
Maximum cores 12 8 8
Maximum SMT
threads per core
8 threads 4 threads 4 threads
Maximum frequency 4.15 GHz 4.4 GHz 4.25 GHz
L2 Cache 512 KB per core 256 KB per core 256 KB per core
L3 Cache 8 MB of FLR-L3 cache
per core with each
core having access to
the full 96 MB of L3
cache, on-chip
eDRAM
10 MB of FLR-L3
cache per core with
each core having
access to the full
80 MB of L3 cache,
on-chip eDRAM
4MB or 8MB of
FLR-L3 cache per core
with each core having
access to the full
32 MB of L3 cache,
on-chip eDRAM
Memory support DDR3 and DDR4 DDR3 DDR3
I/O bus PCIe Gen3 GX++ GX++