Specifications

Chapter 2. Architecture and technical overview 35
Draft Document for Review May 12, 2014 12:46 pm 5102ch02.fm
2.2.1 Custom DIMM (CDIMM)
CDIMMs stand for Custom DIMMs and are an innovative memory DIMMs that do not only
house industry standard DRAM memory chips but also includes a set of components that
allow for higher bandwidth and lower latency communications:
򐂰 Memory Scheduler
򐂰 Memory Management (RAS Decisions & Energy Management)
򐂰 Buffer Cache
By adopting this architecture for the memory DIMMs, several decisions and processes
regarding memory optimizations are executed internally into the CDIMM, saving bandwidth
and allowing for faster processor to memory communications. This also allows for a more
robust RAS. For more information on RAS, refer to Chapter 4, “Continuous availability and
manageability” on page 107.
A detailed diagram of the CDIMM available for the Power S822 can be seen in Figure 2-9.
Figure 2-9 Short CDIMM Diagram
The Buffer Cache is a L4 cache and is built on eDRAM technology (same as L3 cache) which
has lower latency than regular SRAM. Each CDIMM has 16 MB of L4 cache and a fully
populated Power S822 server (2 processor modules and 16 CDIMMs) will have 128 MB of
L4 Cache. The L4 Cache performs several functions that have direct impact in performance
and brings a series of benefits for the Power S822:
򐂰 Reduce energy consumption by reducing the amount of memory requests.
򐂰 Increase memory write performance by acting as a cache and by grouping several random
writes into larger transactions.
򐂰 Partial write operations that target the same cache block will be 'gathered' within the
L4 cache before having to be written to memory, becoming a single write operation.
򐂰 Reduces latency on memory access. Memory access for cached blocks have up to 55%
lower latency than non-cached blocks.