Specifications

Chapter 2. Architecture and technical overview 39
Draft Document for Review May 12, 2014 12:46 pm 5102ch02.fm
SMP interconnect: The POWER8 processor has four 2-byte lanes working at 6.4 GHz with
one spare lane (total 3 active lanes). The bandwidth formula is calculated as follows:
3 lanes * 2 Bytes * 6.4 GHz = 38.4 GBps
2.3 System Bus
This section provides more information related to the internal buses.
The Power S822 systems have internal I/O connectivity through Peripheral Component
Interconnect Express Gen3 (PCI Express Gen3 or PCIe Gen3) slots and also external
connectivity through SAS adapters.
The internal I/O subsystem on the Power S822 is connected to the PCIe Controllers on a
POWER8 processor module in the system. Each POWER8 processor module has a bus that
has 48 PCIe lanes running at 8 Gbps full-duplex and provides 96 GBps of I/O connectivity to
the PCIe slots, SAS internal adapters, and USB ports.
Some PCIe devices are connected directly to the PCIe Gen3 buses on the processors, while
other devices are connected to these buses via PCIe Gen3 Switches. The PCIe Gen3
Switches are high speed devices (ranging from 512 GBps to 768 GBps each) that allow for
the optimal utilization of the processors PCIe Gen3 x16 buses by grouping slower x8 or x4
devices that would plug into a x16 slot and not use its full bandwidth. For more details on
which slots are connected directly to the #and which ones are attached to a PCIe Gen3
Switches (referred as PEX), refer to Chapter 2, “Architecture and technical overview” on
page 23.
A diagram comparing the POWER7 and POWER8 I/O buses architecture can be seen on
Figure 2-11.
Figure 2-11 Comparison of POWER7 & POWER8 I/O buses architectures
Table 2-6 on page 40 lists the I/O bandwidth of Power S822 processor module configurations.