DS-102 Dual Channel RS-232 Asynchronous Communications Adapter for ISA compatible machines INTERFACE CARDS FOR IBM PC/AT AND PS/2 User's Manual QUATECH, INC.
Table of Contents I. GENERAL INFORMATION II. INSTALLATION III. ENABLING AND ADDRESSING PORTS 1 2 4 Setting the address 4 Enabling or disabling ports 6 IV. SETTING INTERRUPT LEVELS (IRQS) Interrupt Sharing V. EXTERNAL CONNECTIONS VI.
WARRANTY INFORMATION Quatech, Inc. warrants the DS-102 to be free of defects for one (1) year from the date of purchase. Quatech, Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights. Please complete the following information and retain for your records.
© 1993, Quatech, Inc. NOTICE The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice.
I. GENERAL INFORMATION The Quatech, Inc. DS-102 provides two RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the ISA (Industry Standard Architecture) expansion bus. The DS-102's two serial ports are implemented using 16450 Universal Asynchronous Receiver/Transmitters (UARTs). For higher performance, 16550 UARTs can be installed in place of the 16450 UARTs. The 16550 contains a hardware buffer that reduces processing overhead.
II. INSTALLATION If the default address and interrupt settings are sufficient, the DS-102 can be quickly installed and put to use. The factory defaults are listed in Figure 1. PORT ADDRESS IRQ ENABLED ? Serial 1 3F8 hex (COM1) 4 YES Serial 2 2F8 hex (COM2) 3 YES Figure 1 --- Default address and IRQ settings for DS-102 The serial port outputs on the DS-102 are CN1 and CN2, which are shielded D-9 connectors. Serial 1 is available on CN1 and Serial 2 is available on CN2. 1.
Set addresses here (SW1, SW2) (Diagram not to scale) 16450/16550 CN1 J1 16450/16550 J2 J3 SW1 Serial 1 J4 Serial 1 J8 Serial 2 SW2 Serial 2 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 J5 Serial 1 J6 Serial 2 QUATECH INC.
III. ENABLING AND ADDRESSING PORTS Setting the address Each serial port on the DS-102 uses 8 consecutive I/O locations in the range of 0000 hex to 07FF hex. The base address of each port is set using a DIP switch pack on the DS-102. When setting the address selection switches, a switch in the "ON" position specifies that the corresponding address line must be a logic 0 for the port to be selected.
Switch on bit = 0 Serial 1 uses SW1 Serial 2 uses SW2 Switch off bit = 1 Factory default setting for Serial 1 --- 03F8 hex (COM1) SW1 ON 1 2 3 4 5 6 7 8 0 2 1 8 4 2 1 8 3 8 F Factory default setting for Serial 2 --- 02F8 hex (COM2) SW2 ON 1 2 3 4 5 6 7 8 0 2 0 8 4 2 1 8 2 8 F Example: 03E8 hex (typical for COM3) ON 1 2 3 4 5 6 7 8 0 2 1 8 4 2 0 8 3 8 E Example: 02E8 hex (typical for COM4) ON 1 2 3 4 5 6 7 8 0 2 0 8 4 2 0 8 2
The standard addresses for serial ports COM1 and COM2 are listed in Figure 5. Recommended addresses for serial ports COM3 and COM4 are also listed. The switch settings for these addresses are shown in Figure 4. PORT TYPICAL I/O ADDRESS NOTES COM1 03F8 hex Factory default for Serial 1. COM2 02F8 hex Factory default for Serial 2. COM3 03E8 hex COM4 02E8 hex Recommendations only. No official standards exist for COM3 and COM4.
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IV. SETTING INTERRUPT LEVELS (IRQS) IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 The DS-102 interrupt circuitry allows each port to use any interrupt level in the range IRQ2 through IRQ7. The interrupt levels are selected using jumper packs J5 for Serial 1 and J6 for Serial 2. In Figure 7, the factory default settings for Serial 1 and Serial 2 are shown.
Interrupt Sharing An interrupt sharing circuit allows a port on the DS-102 to share an interrupt with the other port on the board or with another Quatech adapter supporting sharable interrupts. When interrupt sharing is used, the software must query each port attached to a given IRQ level when an interrupt for that IRQ is received by the computer. Use of this feature is beyond the capabilities of most commercial applications.
V. EXTERNAL CONNECTIONS RS-232-C devices are classified by their function as either Data Terminal Equipment (DTE) or Data Communication Equipment (DCE). Generally, data terminal equipment is defined as the communication source and data communication equipment is defined as the device that provides a communication channel between two DTE-type devices.
To simplify connections to other devices, each port on the DS-102 is equipped with a jumper block that allows the port to be configured as either a DTE- or DCE-type device. This allows the DS-102 to communicate with either DTE- or DCE-type devices without using a null modem cable. J7 is used for Serial 1 and J8 is used for Serial 2. The DTE/DCE selection jumper blocks are illustrated in Figure 12.
The DS-102 connects to peripheral equipment through male D-9 connectors. Adapters are available to convert these connectors into standard D-25 male connectors. The standard serial port connections are listed in Figure 13.
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VI. SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the DS-102. The information presented here is a technical description of the interface to the 16450 or 16550 UART. The 16450 UART is an improved functional equivalent of the 8250 UART, performing serial-to-parallel conversion on received data and parallel-to-serial conversion on output data.
Accessing the Serial Port registers Figure 15 lists the address map for the 16450 and 16550 UARTs. Each register can be accessed by reading from or writing to the proper I/O address. This I/O address is determined by adding an offset to the base address set for the particular serial port. The base address is set using DIP switches on the DS-102 (see section III). Notice that two locations access different registers depending on whether an I/O read or I/O write is attempted.
INTERRUPT ENABLE REGISTER This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.
BIT DESCRIPTION 7 FFE --- FIFO enable: (16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 6 FFE --- FIFO enable: (16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 5 0 --- reserved 4 0 --- reserved 3 IID2 --- Interrupt Identification: IID1 --- Indicates highest priority interrupt pending if any. See Figure 18. NOTE: IID2 is always a logic 0 on the 16450 or in non-FIFO mode IID0 --- on the 16550.
FIFO CONTROL REGISTER (16550 only) This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA. Note that DMA mode is NOT supported by the DS-102 adapter.
LINE CONTROL REGISTER This register is located at I/O address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access to the baud rate divisor latches. BIT DESCRIPTION 7 DLAB --- Divisor latch access bit: DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register.
MODEM CONTROL REGISTER This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send). It is also possible to place the UART in a loopback mode for testing. Finally, the user-defined outputs OUT1 and OUT2 are controlled from this register.
LINE STATUS REGISTER This register is located at I/O address [base+5]. It is used to provide various types of status information concerning the data transfer. As Figure 22 shows, the Line Status Register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break on the receive line. BIT DESCRIPTION 7 FFRX --- Error in RCVR FIFO (16550 FIFO mode only): Always logic 0 in 16450 or 16550 non-FIFO mode.
MODEM STATUS REGISTER This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem. It allows the current states of "modem control signals" to be sensed. These signals include the DCD (Data Carrier Detect), RI (Ring Indicator), DSR (Data Set Ready), and CTS (Clear To Send). The Modem Status Register also provides change information for each of these signals.
FIFO INTERRUPT MODE OPERATION (16550 UART only) When the receiver FIFO and receiver interrupts are enabled: 1. The receive data interrupt is issued when the receive FIFO reaches the trigger level. The interrupt is cleared as soon as the receive FIFO falls below the trigger level. 2. The Interrupt Identification Register's receive data available indicator is set and cleared along with the receive data interrupt when the receive FIFO falls below the trigger level. 3.
FIFO polled mode operation (16550 UART only) The receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced. To use the UART in a polled mode, the software is responsible for continuously checking for the conditions that normally cause interrupts to occur. This would be done using the Line Status Register. 1.
BAUD RATE SELECTION The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the DS-102 uses an 18.432 MHz crystal and a frequency divider circuit to produce the standard clock frequency. Jumper block J1 is used to set the frequency input to the UART.
DESIRED BAUD DIVISOR RATE LATCH VALUE ERROR BETWEEN DESIRED AND ACTUAL VALUES (%) 50 2304 - 75 1536 - 110 1047 0.026 150 768 - 300 384 - 600 192 - 1200 96 - 1800 64 - 2000 58 0.69 2400 48 - 3600 32 - 4800 24 - 7200 16 - 9600 12 - 19200 6 - 38400 3 - 56000 2 2.86 Figure 25 --- Divisor Latch settings for common baud rates using 1.
VII. SPECIFICATIONS Bus interface: Industry Standard Architecture (ISA) 8-bit bus Serial ports Controller: Interface: Transmit drivers: High level output voltage: Low level output voltage: Switching speed: MC1488 or compatible +9V min, +10.5V max -9V min, -10.
VIII. TROUBLESHOOTING Listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact Quatech Customer Service for technical support. Any unauthorized repairs or modifications will void the DS-102's warranty. Computer will not boot up. 1. Is the DS-102 properly inserted? Remove the card and try again. Perhaps try a different expansion slot. 2.
DS-102 Dual Channel RS-232 Asynchronous Communications Adapter User's Manual Revision 3.
