EC C21Hardw warre Des sign n LTEM Module Series S Rev. EC21_Ha ardware_ _Design_ _V1.4 3-01 Date: 2017-03 w www.quectel.
LTE Module Series EC21 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Office 501, Building 13, No.99, Tianzhou Road, Shanghai, China, 200233 Tel: +86 21 5108 6236 Email:info@quectel.com Or our local office.For more information, please visit: http://www.quectel.com/support/salesupport.
LTE Module Series EC21 Hardware Design About the Document History Revision Date Author Description 1.0 2016-04-15 Yeoman CHEN Initial Yeoman CHEN/ Frank WANG/ Lyndon LIU 1. Updated frequency bands in Table 1. 2. Updated transmitting power, supported maximum baud rate of main UART, supported internet protocols, supported USB drivers of USB interface, and temperature range in Table 2. 3. Updated timing of turning on module in Figure 12. 4. Updated timing of turning off module in Figure 13. 5.
LTE Module Series EC21 Hardware Design 6.4. 10. Added note about SIMO in Chapter 6.6. 1. 2. 3. 4. 5. 1.3 2017-01-24 Lyndon LIU/ Rex WANG 6. 7. 8. 9. 10. 1.4 2017-03-01 EC21_Hardware_Design Geely YANG Updated frequency bands in Table 1. Updated function diagram in Figure 1. Updated pin assignment (top view) in Figure 2. Added BT interface in Chapter 3.18.2. Updated reference circuit of wireless connectivity interfaces with FC20 module in Figure 29. Updated GNSS performance in Table 24.
LTE Module Series EC21 Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 4 Table Index .............................................................................................................................................
LTE Module Series EC21 Hardware Design 3.15. STATUS ................................................................................................................................ 50 3.16. Behavior of the RI ................................................................................................................. 51 3.17. SGMII Interface ..................................................................................................................... 51 3.18. Wireless Connectivity Interfaces ...
LTE Module Series EC21 Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF EC21 SERIES MODULE........................................................................ 12 TABLE 2: KEY FEATURES OF EC21 MODULE ............................................................................................... 13 TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 19 TABLE 4: PIN DESCRIPTION ...................................
LTE Module Series EC21 Hardware Design TABLE 42: EC21-A CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 77 TABLE 43: EC21-V CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 77 TABLE 44: EC21-AUT CONDUCTED RF RECEIVING SENSITIVITY ............................................................. 77 TABLE 45: EC21-AUTL CONDUCTED RF RECEIVING SENSITIVITY ......................................................
LTE Module Series EC21 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 18 FIGURE 3: SLEEP MODE APPLICATION VIA UART .......................................................................................
LTE Module Series EC21 Hardware Design FIGURE 37: DIMENSIONS OF THE UF.L-R-SMT CONNECTOR (UNIT: MM) ................................................ 66 FIGURE 38: MECHANICALS OF UF.L-LP CONNECTORS ............................................................................. 66 FIGURE 39: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ........................................................... 67 FIGURE 40: MODULE TOP AND SIDE DIMENSIONS...........................................................................
LTE Module Series EC21 Hardware Design 1 Introduction This document defines the EC21module and describes its air interface and hardware interface which are connected with your application. This document can help you quickly understand module interface specifications, electrical andmechanical details, as well as other related information of EC21 module. Associated with application note and user guide, you can use EC21 module to design and set up mobile applications easily.
LTE Module Series EC21 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating EC21 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, andincorporate these guidelines into all manuals supplied with the product.
LTE Module Series EC21 Hardware Design 2 Product Concept 2.1. General Description EC21 is a series of LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive diversity. It provides data connectivity on LTE-FDD, LTE-TDD,DC-HSPA+, HSPA+, HSDPA, HSUPA, WCDMA,EDGE andGPRSnetworks. It also provides GNSS1) and voice functionality2) for your specific applications.EC21 contains tenvariants:EC21-E, EC21-A, EC21-V, EC21-AUT, EC21-AU,EC21-AUV,EC21-AUTL, EC21-J, EC21-CT and EC21-KL.
LTE Module Series EC21 Hardware Design NOTES 1. 2. 3. 4. 1) 2) GNSS function is optional. EC21 series module (EC21-E, EC21-A, EC21-V, EC21-AUT, EC21-AU,EC21-AUV, EC21-AUTL, EC21-J, EC21-CT and EC21-KL) includes Data-only and Telematics versions. Data-only version does not support voice function, while Telematics version supports it. 3) B2 band on EC21-AU module does not support Rx-diversity. Y = supported (including LTE and WCDMA). N = Not supported. With a compact profile of 32.0mm ×29.0mm ×2.
LTE Module Series EC21 Hardware Design 3GPP R8 CAT24 DC-HSPA+: Max 42Mbps (DL) R99: CSD: 9.6kbps, 14.
LTE Module Series EC21 Hardware Design Baud rate reach up to 3000000bps, 115200bps by default Support RTS and CTS hardware flow control Debug UART: Used for Linux console, log output 115200bps baud rate SGMII Interface Support 10/100/1000Mbps Ethernet connectivity Wireless Connectivity Interfaces Support a low-power SDIO 3.
LTE Module Series EC21 Hardware Design The following figure shows a block diagram of EC21 and illustrates the major functional parts. Power management Baseband DDR+NAND flash Radio frequency Peripheral interfaces ANT_MAIN ANT_GNSS ANT_DIV Switch SAW Switch Duplex LNA SAW VBAT_RF APT PA PRx DRx Tx NAND DDR2 SDRAM Transceiver IQ VBAT_BB PMIC Control Control PWRKEY Baseband RESET_N ADCs 19.
LTE Module Series EC21 Hardware Design 3 Application Interfaces 3.1. General Description EC21 is equipped with 80-pin SMT pads plus 64-pin ground pads and reserved pads that can beconnected to cellular application platform.
LTE Module Series EC21 Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of EC21 module. Figure 2: Pin Assignment (Top View) NOTES 1. 2. 3. 4. 5. 1) means that these pins cannot be pulled up before startup. PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset. Pads 119~126 are SGMII function pins.
LTE Module Series EC21 Hardware Design 6. 7. 8. module. Keep all RESERVEDpins and unused pins unconnected. GND pads 85~112 should be connected to ground in the design, and RESERVED pads 73~84should not be designed in schematic and PCB decal. ※ “ ” means these interface functions are only supported on Telematics version. 3.3. Pin Description The following tables show the pin definition of EC21 module.
LTE Module Series EC21 Hardware Design VDD_EXT 7 PO GND 8,9,19,22,3 6,46,48,50 ~54,56,72, 85~112 Provide 1.8V for external circuit Vnorm=1.8V IOmax=50mA Power supply for external GPIO’s pull up circuits. Ground Turn on/off Pin Name Description DC Characteristics Comment Turnon/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.8V because of the diode drop in the Qualcomm chipset. DI Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.
LTE Module Series EC21 Hardware Design USIM Interface Pin Name Pin No. USIM_GND 10 I/O Description DC Characteristics Specified ground for USIM card For 1.8V USIM: Vmax=1.9V Vmin=1.7V USIM_VDD USIM_DATA USIM_CLK USIM_RST USIM_ PRESENCE 14 15 16 17 13 EC21_Hardware_Design Comment PO IO DO DO DI Power supply for USIM card Data signal of USIM card Clock signal of USIM card Reset signal of USIM card USIM card insertion detection For 3.0V USIM: Vmax=3.05V Vmin=2.
LTE Module Series EC21 Hardware Design UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment RI 62 DO Ring indicator VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DCD 63 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. CTS 64 DO Clear to send VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.
LTE Module Series EC21 Hardware Design PCM Interface Pin Name Pin No. I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep it open. PCM_IN 24 DI PCM data input VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_OUT 25 DO PCM data output VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. PCM data frame synchronization signal VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
LTE Module Series EC21 Hardware Design EPHY_INT_N SGMII_ MDATA SGMII_ MCLK 120 121 122 DI IO DO Ethernet PHY interrupt SGMII MDIO (Management Data Input/Output) data SGMII MDIO (Management Data Input/Output) clock VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V For 1.8V: VOLmax=0.45V VOHmin=1.4V VILmax=0.58V VIHmin=1.27V For 2.85V: VOLmax=0.35V VOHmin=2.14V VILmax=0.71V VIHmin=1.78V For 1.8V: VOLmax=0.45V VOHmin=1.4V For 2.85V: VOLmax=0.35V VOHmin=2.14V 1.8V power domain.
LTE Module Series EC21 Hardware Design VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V SDC1_ DATA2 SDC1_ DATA1 SDC1_ DATA0 SDC1_CLK SDC1_CMD PM_ENABLE WAKE_ON_ WIRELESS WLAN_EN 130 131 132 133 134 127 135 136 COEX_UART_ 137 RX EC21_Hardware_Design open. SDIO data bus D2 VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. SDIO data bus D1 VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.
LTE Module Series EC21 Hardware Design COEX_UART_ 138 TX DO LTE/WLAN coexistence signal WLAN_SLP_ CLK DO WLAN sleep clock 118 VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. If unused, keep it open. DI BT UART request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. DO BT UART transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DI BT UART data VILmin=-0.3V VILmax=0.6V VIHmin=1.
LTE Module Series EC21 Hardware Design control AP_READY 2 VILmax=0.6V VIHmin=1.2V VIHmax=2.0V Pull-up by default. In low voltage level, module can enter into airplane mode. If unused, keep it open. DI Application processor sleep state detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. I/O Description DC Characteristics Comment DI Force the module to boot from USB port. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
LTE Module Series EC21 Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 5: Overview of Operating Modes Mode Normal Operation Details Idle Software is active. The module hasbeen registered onthe network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network settingand data transfer rate.
LTE Module Series EC21 Hardware Design The following figure shows the connection between the module and the host. Figure 3: Sleep Mode Application via UART Driving thehost DTR to low level will wake up the module. When EC21 has URC to report, RI signal will wake up the host. Refer to Chapter 3.16 for details about RI behavior. AP_READY will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG=“apready”command for details.
LTE Module Series EC21 Hardware Design The following figure shows the connection between the module and the host. Figure 4: Sleep Mode Application withUSB Remote Wakeup Sending data to EC21through USB will wake up the module. When EC21has URC to report, the module will send remote wake-up signals via USB bus so as to wake up the host. 3.5.1.3.
LTE Module Series EC21 Hardware Design The following figure shows the connection between the module and the host. Figure 5: Sleep Mode Application with RI Sending data to EC21through USB will wake up the module. When EC21has URC to report, RI signal will wake up the host. 3.5.1.4. USB Application without USB Suspend Function If the host does not support USB suspend function, you should disconnect USB_VBUS with additional control circuit to let the module enter into sleep mode.
LTE Module Series EC21 Hardware Design Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and thehost.Refer to document [1] for more details about EC21 power management application. 3.5.2. Airplane Mode When the module enters into airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. This mode can be set via the following ways.
LTE Module Series EC21 Hardware Design Table 6: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_RF 57,58 Power supply for module RF part. 3.3 3.8 4.3 V VBAT_BB 59,60 Power supply for module baseband part. 3.3 3.8 4.3 V GND 8,9,19,22,36,46 , 48,50~54,56, 72, 85~112 Ground - 0 - V 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3Vto4.3V. Please make sure that the input voltage will never drop below 3.3V.
LTE Module Series EC21 Hardware Design Figure 8: Star Structure of the Power Supply 3.6.3. Reference Design for Power Supply Power design for the module is very important, asthe performance of the module largely depends on the power source. The power supply is capable of providing sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, it is suggested that you shoulduse an LDO to supply power for the module.
LTE Module Series EC21 Hardware Design 3.6.4. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. 3.7. Turn on and off Scenarios 3.7.1. Turn on Module Using the PWRKEY The following table shows the pin definition of PWRKEY. Table 7: PWRKEY Pin Description Pin Name PWRKEY Pin No. 21 Description DC Characteristics Comment Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.
LTE Module Series EC21 Hardware Design Figure 11: Turn on the Module Using Keystroke The turn on scenario is illustrated in the following figure. Figure 12: Timing of Turning on Module NOTE Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms.
LTE Module Series EC21 Hardware Design 3.7.2. Turn off Module The following procedures can be used to turn off the module: Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using AT+QPOWD command. 3.7.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltagefor at least 650ms, the module will execute power-down procedure after the PWRKEY is released.
LTE Module Series EC21 Hardware Design 3.8. Reset the Module The RESET_N pin can be used to reset the module.The module can be reset by driving RESET_N to a low level voltage for time between 150ms and 460ms. Table 8: RESET_N Pin Description Pin Name RESET_N Pin No. 20 Description DC Characteristics Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Comment The recommended circuit is similar to the PWRKEY control circuit.
LTE Module Series EC21 Hardware Design The reset scenario is illustrated inthe following figure. Figure 16: Timing of Resetting Module NOTES 1. 2. Use RESET_N only when turning off the module by AT+QPOWD command and PWRKEY pin failed. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. 3.9. USIM Card Interface The USIM card interface circuitrymeets ETSI and IMT-2000 SIM interface requirements. Both 1.8V and 3.0V USIM cards are supported.
LTE Module Series EC21 Hardware Design EC21 supports USIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET command for details. The following figure shows a reference design for USIM card interface with an 8-pin USIM card connector.
LTE Module Series EC21 Hardware Design In order to enhance the reliability and availability of the USIM card in your application, please follow the criteria below in USIM circuit design: Keep layout of USIM card as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep USIM card signals away from RF and VBAT traces. Assure the ground between the module and the USIM card connectorshort and wide. Keep the trace width of ground and USIM_VDD no less than 0.
LTE Module Series EC21 Hardware Design The USB interface is recommended to be reserved for firmware upgrade in your design. The following figure shows areference circuit of USB interface. Figure 19: Reference Circuit of USB Application In order to ensurethe integrity of USB data line signal, components R1, R2, R3 and R4 must be placed close to the module, and alsothese resistors should be placed close to each other. The extra stubs of trace must be as short as possible.
LTE Module Series EC21 Hardware Design 3.11. UART Interfaces The module provides two UART interfaces: the main UART interface and the debug UART interface. The following shows their features. The main UART interface supports 4800, 9600,19200,38400, 57600,115200,230400,460800,921600and 3000000bps baud rates, and the default is 115200bps. The interface is used for data transmission and AT command communication. The debug UART interface supports 115200bpsbaud rate.
LTE Module Series EC21 Hardware Design Table 13:Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V The module provides 1.8V UART interface. A level translator should be used if your application is equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrumentis recommended. The following figure shows areference design. Figure 20: Reference Circuit with Translator Chip Please visithttp://www.
LTE Module Series EC21 Hardware Design Figure 21: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12.
LTE Module Series EC21 Hardware Design Figure 22: Primary Mode Timing Figure 23: Auxiliary Mode Timing The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio codec design. Table 14: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_IN 24 DI PCM data input 1.8V power domain PCM_OUT 25 DO PCM data output 1.8V power domain PCM_SYNC 26 IO PCM data frame sync signal 1.
LTE Module Series EC21 Hardware Design PCM_CLK 27 IO PCM data bit clock 1.8V power domain I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V Clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048kHzPCM_CLK and 8kHz PCM_SYNC.Please refer to document [2] about AT+QDAIcommand for details.
LTE Module Series EC21 Hardware Design 3.13. ADC Function The module provides two analog-to-digital converters (ADC).AT+QADC=0 command can be used to read the voltage value on ADC0 pin. AT+QADC=1command can be used to read the voltage value on ADC1 pin. For more details about these AT commands, please refer todocument [2]. In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground. Table 15: Pin Definition of the ADC Pin Name Pin No.
LTE Module Series EC21 Hardware Design 3.14. Network Status Indication The network indication pins can be used to drive network status indicationLEDs. The module provides two pins which are NET_MODE and NET_STATUS. The following tables describe thepin definition and logic level changes in different network status. Table 17: Pin Definition of Network ConnectionStatus/Activity Indicator Pin Name Pin No.
LTE Module Series EC21 Hardware Design Figure 25: Reference Circuit of the Network Indicator 3.15. STATUS The STATUS pin is an open drain output for indicating the module’s operation status. You can connect it to a GPIO of DTE with a pull up resistor, or as the LED indication circuit shown below. When the module is turned on normally, the STATUS will present the low state. Otherwise, the STATUS will present high-impedance state. Table 19: Pin Definition of STATUS Pin Name STATUS Pin No.
LTE Module Series EC21 Hardware Design 3.16. Behavior of the RI AT+QCFG=“risignaltype”,“physical” command can be usedto configure RI behavior. No matter on which port URC is presented, URC will trigger the behavior of RI pin. NOTE URC can be output from UART port, USB AT port and USB modem port by AT+QURCCFG command. The default port is USB AT port. In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below.
LTE Module Series EC21 Hardware Design Table 21: Pin Definition of the SGMII Interface Pin Name Pin No. I/O Description Comment EPHY_RST_N 119 DO Ethernet PHY reset 1.8V/2.85V power domain EPHY_INT_N 120 DI Ethernet PHY interrupt 1.8V power domain SGMII_MDATA 121 IO SGMII MDIO (Management Data Input/Output) data 1.8V/2.85V power domain SGMII_MCLK DO SGMII MDIO (Management Data Input/Output) clock 1.8V/2.85V power domain PO SGMII MDIO pull-up power source Configurable power source.
LTE Module Series EC21 Hardware Design Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application In order to enhance the reliability and availability in your application, please follow the criteria below in the Ethernet PHY circuit design: Keep SGMII data and control signals away from RF and VBAT trace. Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than 20mil. The differential impedance of SGMII data trace is 100ohm±10%.
LTE Module Series EC21 Hardware Design 3.18. Wireless Connectivity Interfaces EC21supports a low-power SDIO 3.0 interface for WLAN and a UART/PCM interface for BT. The following table shows the pin definition of wireless connectivity interfaces. Table 22: Pin Definition of Wireless Connectivity Interfaces Pin Name Pin No. I/O Description Comment SDC1_DATA3 129 IO SDIO data bus D3 1.8V power domain SDC1_DATA2 130 IO SDIO data bus D2 1.8V power domain SDC1_DATA1 131 IO SDIO data bus D1 1.
LTE Module Series EC21 Hardware Design BT_CTS* 40 DO BT UART clear to send 1.8V power domain PCM_IN1) 24 DI PCM data input 1.8V power domain PCM_OUT1) 25 DO PCM data output 1.8V power domain PCM_SYNC1) 26 IO PCM data frame sync signal 1.8V power domain PCM_CLK1) 27 IO PCM data bit clock 1.8V power domain BT_EN* 139 DO WLAN function control via FC20 module. Active high. 1.8V power domain NOTES 1. “*” means under development. 2.
LTE Module Series EC21 Hardware Design NOTES 1. 2. 3. FC20 module can only be used as a slave device, When BT function is enabled on EC21 module, PCM_SYNC and PCM_CLK pins are only used to output signals. For more information about wireless connectivity interfaces, please refer to document [5]. 3.18.1. WLAN Interface EC21 provides a low power SDIO 3.0 interface and control interface for WLAN design.
LTE Module Series EC21 Hardware Design 3.19. USB_BOOT Interface EC21 provides a USB_BOOT pin. During development or factory production, USB_BOOT pin can force the module to boot from USB port for firmware upgrade. Table 23: Pin Definition of USB_BOOT Interface Pin Name USB_BOOT Pin No. 115 I/O Description Comment DI Force the module to boot from USB port 1.8V power domain. Active high. If unused, keep it open. The following figure shows a reference circuit of USB_BOOT interface.
LTE Module Series EC21 Hardware Design 4 GNSS Receiver 4.1. General Description EC21 includes a fully integrated global navigation satellite system solution that supports Gen8C-Liteof Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EC21 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update ratevia USB interface by default. By default, EC21 GNSS engine is switched off. It has to be switched on via AT command.
LTE Module Series EC21 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous 2.5 s XTRA enabled 1.8 s Autonomous @open sky <1.5 m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
LTE Module Series EC21 Hardware Design 5 Antenna Interfaces EC21 antenna interfaces include a main antennainterface,anRx-diversity antenna interface which is used toresist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna interface. The antenna interfaceshave an impedance of 50ohm. 5.1. Main/Rx-diversityAntenna Interface 5.1.1. Pin Definition The pin definition of main antenna and Rx-diversityantenna interfacesis shown below.
LTE Module Series EC21 Hardware Design B12 699~716 729~746 MHz B13 777~787 746~756 MHz B18 815~830 860~875 MHz B19 830~845 875~890 MHz B20 832~862 791~821 MHz B26 814~849 859~894 MHz B28 703~748 758~803 MHz B40 2300~2400 2300~2400 MHz 5.1.3. Reference Design of RF Antenna Interface Areference design of ANT_MAIN and ANT_DIVantenna pads is shown as below. It should reserve a π-type matching circuit for better RF performance. The capacitors are not mounted by default.
LTE Module Series EC21 Hardware Design 5.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50 ohm. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control.
LTE Module Series EC21 Hardware Design Figure 34: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use impedance simulation tool to control the characteristic impedanceof RF tracesas 50ohm.
LTE Module Series EC21 Hardware Design 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. Table 27: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 47 AI GNSS antenna 50ohmimpedance Table 28: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz BeiDou 1561.098±2.046 MHz A reference design of GNSS antenna is shown as below.
LTE Module Series EC21 Hardware Design 5.3. Antenna Installation 5.3.1. Antenna Requirement The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna. Table 29: Antenna Requirements Type Requirements GNSS Frequency range: 1561~1615MHz Polarization: RHCP or linear VSWR: <2 (Typ.) Passive antenna gain: >0dBi Active antenna noise figure: <1.5dB Active antenna gain: >-2dBi Active antenna embedded LNA gain: 20dB (Typ.) Active antenna total gain: >18dBi (Typ.
LTE Module Series EC21 Hardware Design 5.3.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use UF.L-R-SMT connector provided by HIROSE. Figure 37: Dimensions of the UF.L-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the UF.L-R-SMT. Figure 38:Mechanicalsof UF.
LTE Module Series EC21 Hardware Design The following figure describes the space factor of mated connector. Figure39:Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
LTE Module Series EC21 Hardware Design 6 Electrical, Reliability and RadioCharacteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 1.8 A Voltage at Digital Pins -0.3 2.
LTE Module Series EC21 Hardware Design VBAT_RF min/max values, including voltage drop, ripple and spikes. Voltage drop during burst transmission Maximum power control level on GSM900 IVBAT Peak supply current (during transmissionslot) Maximum power control level on GSM900 USB_VBUS USB detection 3.0 400 mV 1.8 2.0 A 5.0 5.25 V 6.3. Operating Temperature The operating temperature is listed in the following table. Table 32: Operating Temperature Parameter Min. Typ. Max.
LTE Module Series EC21 Hardware Design 6.4. Current Consumption The values of current consumption are shown below. Table 33: EC21-A Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 20 uA AT+CFUN=0 (USB disconnected) 1.0 mA WCDMA PF=64 (USB disconnected) 2.8 mA WCDMA PF=128 (USB disconnected) 2.3 mA LTE-FDD PF=64 (USB disconnected) 2.2 mA LTE-FDD PF=128 (USB disconnected) 2.2 mA WCDMA PF=64 (USB disconnected) 21.
LTE Module Series EC21 Hardware Design WCDMA B4 @23.36dBm 594.0 mA WCDMA B5 @23.64dBm 522.0 mA Table 34: EC21-AUT Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 20 uA AT+CFUN=0 (USB disconnected) 0.99 mA WCDMA PF=64 (USB disconnected) 2.1 mA WCDMA PF=128 (USB disconnected) 1.7 mA LTE-FDD PF=64 (USB disconnected) 2.9 mA LTE-FDD PF=128 (USB disconnected) 2.4 mA WCDMA PF=64 (USB disconnected) 22.0 mA WCDMA PF=64 (USB connected) 32.
LTE Module Series EC21 Hardware Design Table 35: EC21-E Current Consumption Parameter Description Conditions Typ.
LTE Module Series EC21 Hardware Design WCDMA datatransfer(GNSS OFF) LTE datatransfer(GNSS OFF) DCS1800 1DL/4UL @25dBm 430 mA WCDMA B1 HSDPA@22.5dBm 659 mA WCDMA B1 HSUPA@21.11dBm 545 mA WCDMA B5 HSDPA@23.5dBm 767 mA WCDMA B5 HSUPA@21.4dBm 537 mA WCDMA B8 HSDPA@22.41dBm 543 mA WCDMA B8 HSUPA@21.2dBm 445 mA LTE-FDD B1 @23.45dBm 807 mA LTE-FDD B3 @23.4dBm 825 mA LTE-FDD B5 @23.4dBm 786 mA LTE-FDD B7 @23.86dBm 887 mA LTE-FDD B8 @23.5dBm 675 mA LTE-FDD B20 @23.
LTE Module Series EC21 Hardware Design LTE datatransfer(GNSS OFF) LTE-FDD B1 @23.65dBm 765.0 mA LTE-FDD B3 @23.2dBm 825.0 mA LTE-FDD B5 @23.2dBm 598.0 mA LTE-FDD B7 @23.7dBm 762.0 mA LTE-FDD B8 @23.1dBm 569.0 mA Table 37: EC21-V Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 20 uA AT+CFUN=0 (USB disconnected) 1.0 mA LTE-FDD PF=64 (USB disconnected) 2.5 mA LTE-FDD PF=128 (USB disconnected) 2.
LTE Module Series EC21 Hardware Design WCDMA datatransfer(GNSS OFF) LTE datatransfer(GNSS OFF) WCDMA voice call LTE-FDD PF=64 (USB disconnected) 24.0 mA LTE-FDD PF=64 (USB connected) 34.0 mA WCDMA B1 HSDPA@22.05dBm 586.0 mA WCDMA B1 HSUPA@22.29dBm 630.0 mA WCDMA B5 HSDPA@22.43dBm 576.0 mA WCDMA B5 HSUPA@22.43dBm 600.0 mA WCDMA B8 HSDPA@22.44dBm 577.0 mA WCDMA B8 HSUPA@21.78dBm 555.0 mA LTE-FDD B1 @23.12dBm 721.0 mA LTE-FDD B3 @23.04dBm 734.0 mA LTE-FDD B5 @23.16dBm 669.
LTE Module Series EC21 Hardware Design 6.5. RF Output Power The following table shows the RF output power of EC21 module. Table 40: RF Output Power Frequency Max. Min. GSM900 33dBm±2dB 5dBm±5dB DCS1800 30dBm±2dB 0dBm±5dB DCS1800 26dBm±3dB 0dBm±5dB WCDMA bands 22.5dBm+1/-3dB <-50dBm LTE-FDD bands 22.5dBm+1/-3dB <-44dBm LTE-TDD bands 22.5dBm+1/-3dB <-44dBm NOTE In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0dB.
LTE Module Series EC21 Hardware Design LTE-FDD B1(10M) -98.0dBm -98.0dBm -101.5dBm -96.3dBm LTE-FDD B3(10M) -96.5dBm -98.5dBm -101.5dBm -93.3dBm LTE-FDD B5(10M) -98.0dBm -98.5dBm -101.0dBm -94.3dBm LTE-FDD B7(10M) -97.0dBm -94.5dBm -99.5dBm -94.3dBm LTE-FDD B8(10M) -97.0dBm -97.0dBm -101.0dBm -93.3dBm LTE-FDD B20(10M) -97.5dBm -99.0dBm -102.5dBm -93.3dBm Table 42: EC21-A Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 3GPP (SIMO) WCDMA B2 -110.
LTE Module Series EC21 Hardware Design LTE-FDD B1(10M) -98.5dBm -98.0dBm -101.0dBm -96.3dBm LTE-FDD B3(10M) -98.0dBm -96.0dBm -100.0dBm -93.3dBm LTE-FDD B5(10M) -98.0dBm -99.0dBm -102.5dBm -94.3dBm LTE-FDD B7(10M) -97.0dBm -95.0dBm -98.5dBm -94.3dBm LTE-FDD B28(10M) -97.0dBm -99.0dBm -102.0dBm -94.8dBm Table 45: EC21-AUTL Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 3GPP (SIMO) LTE-FDD B3(10M) -98.0dBm -96.0dBm -100.0dBm -93.
LTE Module Series EC21 Hardware Design Table 48: EC21-J Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 3GPP (SIMO) LTE-FDD B1 (10M) -97.5dBm -98.7dBm -100.2dBm -96.3dBm LTE-FDD B3 (10M) -96.5dBm -97.1dBm -100.5dBm -93.3dBm LTE-FDD B8 (10M) -98.4dBm -99.0dBm -101.2dBm -93.3dBm LTE-FDD B18 (10M) -99.5dBm -99.0dBm -101.7dBm -96.3dBm LTE-FDD B19 (10M) -99.2dBm -99.0dBm -101.4dBm -96.3dBm LTE-FDD B26 (10M) -99.5dBm -99.0dBm -101.5dBm -93.
LTE Module Series EC21 Hardware Design 6.7. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the module’s electrostatic discharge characteristics.
LTE Module Series EC21 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module.All dimensions are measured in mm. 7.1. Mechanical Dimensions of the Module 2.4+/-0.2 (29+/-0.15) (32+/-0.15) 0.
LTE Module Series EC21 Hardware Design 32.0 1.30 3.85 3.5 1.90 3.35 5.96 1.30 2.0 2.0 0.82 3.0 1.15 2.15 1.8 2.8 29.0 1.8 4.88 1.05 1.10 1.6 4.8 6.75 1.10 1.7 2.49 1.9 2.4 3.45 3.2 3.4 3.2 3.4 0.8 3.2 3.5 4.4 1.
LTE Module Series EC21 Hardware Design 7.2. Recommended Footprint 24.70 1.80 1.10 3.00 2.00 2.00 1.10 7.80 1.90 3.45 3.40 3.85 2.00 4.80 1.80 3.00 0.50 2.80 0.50 4.80 0.50 4.80 Keepout area 15.60 0.50 3.50 1.90 3.20 1.30 3.40 3.20 3.40 3.20 32.0 3.40 4.80 0.80 2.50 1.00 Figure42: Recommended Footprint (Top View) NOTES 1. 2. The keepout area should not be designed.
LTE Mod dule Series s EC C21 Hardw ware Design n 7.3. Design Effec ct Drawin ngsof the Module e Figure43: Top T Viewof the Module e Fig gure 44: Bo ottom View of the Module NOTE Thesearede esign effect drawings off EC21 modu ule. For morre accurate pictures, ple ease refer to o the module e that you gett from Quecttel.
LTE Module Series EC21 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EC21 is stored in a vacuum-sealed bag. The storage restrictionsareshown as below. 1. Shelf life in thevacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bagis opened, devices that will be subjected to reflow soldering or other high temperature processes must be: Mounted within 72 hours at the factory environment of ≤30ºC/60%RH Stored at <10%RH 3.
LTE Module Series EC21 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properlyso as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, thethickness of stencil for the module is recommended to be 0.18mm. For more details, please refer todocument [4].
LTE Module Series EC21 Hardware Design 8.3. Packaging .1 ±0 50 . 1 30.3± 0.15 0.35± 0.05 29.3± 0.15 44.00± 0.3 20.20± 0.15 44.00± 0.1 2.00± 0.1 4.00± 0.1 30.3± 0.15 1.75± 0.1 EC21 is packaged in tape andreel carriers. One reel is 11.53m longand contains 250pcs modules. The figure below shows the packagingdetails, measured in mm. 4.2± 0.15 3.1± 0.15 32.5± 0.15 33.5± 0.15 32.5± 0.15 33.5± 0.15 e p a t r e v o C 48.5 13 100 d e e f f o n o i t c e r i D 44.5+0.20 -0.
LTE Module Series EC21 Hardware Design 9 Appendix A References Table 51: Related Documents SN Document Name Remark [1] Quectel_EC21_Power_Management_Application_Note EC21 Power Management Application Note [2] Quectel_EC25&EC21_AT_Commands_Manual EC25 and EC21 AT Commands Manual [3] Quectel_EC25&EC21_GNSS_AT_Commands_Manual EC25 and EC21GNSS AT Commands Manual [4] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide [5] Quectel_EC21_Reference_Design EC21 Reference Desig
LTE Module Series EC21 Hardware Design DL Downlink DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnayaNAvigatsionnayaSputnikovayaSistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GNSS Global Navigation Satellite System GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packe
LTE Module Series EC21 Hardware Design PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media IndependentInterface SIM Subscriber Identification Module SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing TDMA Time Division
LTE Module Series EC21 Hardware Design VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WCDMA Wide
LTE Module Series EC21 Hardware Design 10 Appendix B GPRS Coding Schemes Table 53: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
LTE Module Series EC21 Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
LTE Mo odule Sires s EC C21 Hardw ware Design n 12 Apppendixx D EDGE E E Mod dulationan nd Cod ding Schem S mes E Modu ulation and Coding Sch hemes Table 55: EDGE Coding Sch heme Mod dulation Coding Family 1 Timeslot 2 Tim meslot 4 Timeslot CS-1: GMSK / 9.05kbps 9 18.1kkbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kkbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kkbps 62.4kbps CS-4: GMSK / 21.4kbps 2 42.8kkbps 85.6kbps MCS-1 GMSK C 8.80kbps 8 17.60 0kbps 35.20kbps MCS-2 GMSK B 11.
