Product Info
Table Of Contents
- About the Document
- Contents
- Table Index
- Figure Index
- Introduction
- Product Concept
- Application Interfaces
- GNSS Receiver
- Antenna Interfaces
- Electrical, Reliability and RadioCharacteristics
- Mechanical Dimensions
- Storage, Manufacturing and Packaging
- Appendix A References
LTE Module Series
EG61-NA Hardware Design
EG61-NA_Hardware_Design 43 / 77
Table 11: Pin Definition of Main UART Interface
Pin Name
Pin No. I/O Description Comment
RI 39 DO Ring indicator
1.8V power domain
DCD 38 DO Data carrier detection
CTS 36 DO Clear to send
RTS 37 DI Request to send
DTR 30 DI Sleep mode control
TXD 35 DO Transmit data
RXD 34 DI Receive data
Table 12: Pin Definition of Debug UART Interface
Pin Name Pin No. I/O Description Comment
DBG_TXD 23 DO Transmit data 1.8V power domain
DBG_RXD 22 DI Receive data 1.8V power domain
The logic levels are described in the following table.
Table 13:Logic Levels of Digital I/O
Parameter Min. Max. Unit
V
IL
-0.3 0.6 V
V
IH
1.2 2.0 V
V
OL
0 0.45 V
V
OH
1.35 1.8 V
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is
recommended. The following figure shows areference design.