Product Info

LTE Module Series
AG35-QuecOpen
Hardware Design
AG35-Quecopen_Hardware_Design 36 / 137
PM_ENABLE 5 PM_ENABLE
PMU_
GPIO_03
-- -- B-PD,L Low level NO
SDC1_CMD 18 SDC1_CMD GPIO_17
UART_RXD_
BLSP4
-- B-PD,L Low level YES
SDC1_CLK 19 SDC1_CLK GPIO_16
UART_TXD_
BLSP4
-- B-NP,L Low level YES
SDC1_DATA0 20 SDC1_DATA0 GPIO_15
UART_CTS_
BLSP1
SPI_CLK_
BLSP1
B-PD,L Low level NO
SDC1_DATA1 21 SDC1_DATA1 GPIO_14
UART_RTS_
BLSP1
SPI_CS_N
_BLSP1
B-PD,L Low level NO
SDC1_DATA2 22 SDC1_DATA2 GPIO_13
UART_RXD_
BLSP1
SPI_MISO
_BLSP1
B-PD,L Low level YES
SDC1_DATA3 23 SDC1_DATA3 GPIO_12
UART_TXD_
BLSP1
SPI_MOSI
_BLSP1
B-PD,L Low level YES
USIM_
PRESENCE
25
USIM_
PRESENCE
GPIO_34 -- -- B-PD,L Low level YES
I2C1_SDA 42
I2C_SDA_
BLSP4
GPIO_18 -- -- B-PD,L High level NO
I2C1_SCL 43
I2C_SCL_
BLSP4
GPIO_19 -- -- B-PD,L High level NO
SDC2_INT_
DET
52
SDC2_INT_
DET
GPIO_26 -- -- B-PD,L Low level YES
UART1_CTS 56
UART_CTS_
BLSP3
GPIO_3
SPI_CLK_BL
SP3
-- B-PD,L Low level YES
UART1_RTS 57
UART_RTS_
BLSP3
GPIO_2
SPI_CS_N_B
LSP3
-- B-PD,L Low level NO