Product Info

LTE Module Series
AG35-QuecOpen
Hardware Design
AG35-Quecopen_Hardware_Design 37 / 137
UART1_RXD 58
UART_RXD_
BLSP3
GPIO_1
SPI_MISO_B
LSP3
-- B-PD,L Low level YES
UART1_TXD 60
UART_TXD_
BLSP3
GPIO_0
SPI_MOSI_B
LSP3
-- B-PD,L Low level NO
PCM_SYNC 65 PCM_SYNC GPIO_79 -- -- B-PD,L Low level YES BOOT_CONFIG_7
PCM_IN 66 PCM_IN GPIO_76 -- -- B-PD,L Low level YES
PCM_CLK 67 PCM_CLK GPIO_78 -- -- B-PD,L Low level NO BOOT_CONFIG_8
PCM_OUT 68 PCM_OUT GPIO_77 -- -- B-PD,L Low level NO
I2C2_SDA 73
I2C_SDA_
BLSP2
GPIO_6 -- -- B-PD,L High pulse NO
Recommended to be “input”.
Please refer to NOTE 3 for
details.
I2C2_SCL 74
I2C_SCL_
BLSP2
GPIO_7 -- -- B-PD,L Low level NO
SPI_MOSI 77
SPI_MOSI_
BLSP6
GPIO_20
UART_TXD_
BLSP6
PCM_1A_
SYNC
B-PD,L Low level YES
SPI_MISO 78
SPI_MISO_
BLSP6
GPIO_21
UART_RXD_
BLSP6
PCM_1A
_IN
B-PD,L Low level YES
SPI_CS_N 79
SPI_CS_N_
BLSP6
GPIO_22
UART_RTS_
BLSP6
PCM_1A
_OUT
B-PD,L Low level YES
SPI_CLK 80
SPI_CLK_
BLSP6
GPIO_23
UART_CTS_
BLSP6
PCM_1A
_CLK
B-PU,H High level NO BOOT_CONFIG_4
WLAN_EN 149 WLAN_EN GPIO_54 -- -- B-PD,L Low level NO BOOT_CONFIG_6
UART2_TXD 163
UART_TXD_B
LSP5
GPIO_8
SPI_MOSI_B
LSP5
-- B-PD,L Low level YES