Product Info

LTE Module Series
AG35-QuecOpen
Hardware Design
AG35-Quecopen_Hardware_Design 38 / 137
1. The pin functions in Mode 2/3/4 take effect only after software configuration.
2. Pins 150, 159 and 143 are recommended to be “output” when they are used as GPIOs. When they are used as “input”, they should be configured as NP
(no pull-up or pull-down internally) and add pull-up/pull-down circuits externally.
3. The module will generate a high pulse on pin 73 during power-up. Therefore, when pin 73 is used as GPIO, it is recommended to use it as “input”.
4.
1)
Please refer to Table 3 for more details about the symbol description.
5.
2)
If the GPIOs of no interrupt function configured as interrupter function, it will increase consumption of the module. (“YES” means “interrupt function
supported”. “NO” means “interrupt function not supported”.)
6. Pins 59, 65, 67, 144~147, 149 and 159 cannot be pulled up before power-up. Pin 80 cannot be pulled down before power-up.
7. “*” means under development.
The following table lists the pull-up and pull-down resistance values of AG35-Quecopen GPIOs.
UART2_CTS 164
UART_CTS_B
LSP5
GPIO_11
SPI_CLK_BL
SP5
-- B-PU,L High level YES
UART2_RXD 165
UART_RXD_
BLSP5
GPIO_9
SPI_MISO_B
LSP5
-- B-PD,L Low level YES
UART2_RTS 166
UART_RTS_B
LSP5
GPIO_10
SPI_CS_N_B
LSP5
-- B-PD,L Low level NO
WLAN_SLP_
CLK
169
WLAN_SLP_
CLK
PMU_
GPIO_06
-- -- B-PD,L Low level NO
NET_STATUS 170
PMU_GPIO_0
1
NET_STA
TUS
-- -- B-PD,L Low level NO
NOTES