Product Info

LTE Module Series
AG35-Quecopen
Hardware Design
AG35-QuecOpen_Hardware_Design 8 / 137
Table Index
TABLE 1: FREQUENCY BANDS OF AG35-QUECOPEN MODULES .............................................................. 15
TABLE 2: KEY FEATURES OF AG35-QUECOPEN MODULES ...................................................................... 15
TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 23
TABLE 4: PIN DESCRIPTION ........................................................................................................................... 24
TABLE 5: ALTERNATE FUNCTIONS OF MULTIPLEXING PINS ..................................................................... 35
TABLE 6: PULL-UP/PULL-DOWN RESISTANCE OF GPIOS .......................................................................... 39
TABLE 7: OVERVIEW OF OPERATING MODES ............................................................................................. 40
TABLE 8: VBAT AND GND PINS ....................................................................................................................... 44
TABLE 9: PWRKEY PIN DESCRIPTION .......................................................................................................... 46
TABLE 10: PIN DEFINITION OF SHDN_N ....................................................................................................... 50
TABLE 11: RESET_N PIN DESCRIPTION ....................................................................................................... 51
TABLE 12: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 53
TABLE 13: PIN DESCRIPTION OF USB INTERFACE ..................................................................................... 55
TABLE 14: PIN DEFINITION OF UART1 INTERFACE ..................................................................................... 57
TABLE 15: PIN DEFINITION OF UART2 INTERFACE ..................................................................................... 57
TABLE 16: PIN DEFINITION OF UART3 INTERFACE (MULTIPLEXED FROM SPI) ...................................... 57
TABLE 17: PIN DEFINITION OF UART4 INTERFACE (MULTIPLEXED FROM SDIO1) ................................. 58
TABLE 18: PIN DEFINITION OF UART5 INTERFACE (MULTIPLEXED FROM SDIO1) ................................. 58
TABLE 19: PIN DEFINITION OF DEBUG UART INTERFACE ......................................................................... 58
TABLE 20: LOGIC LEVELS OF DIGITAL I/O .................................................................................................... 59
TABLE 21: PIN DEFINITION OF ANALOG AUDIO INTERFACE ...................................................................... 60
TABLE 22: PIN DEFINITION OF PCM INTERFACE ......................................................................................... 63
TABLE 23: PIN DEFINITION OF I2C INTERFACES ......................................................................................... 63
TABLE 24: PIN DEFINITION OF SDIO2 INTERFACE ...................................................................................... 65
TABLE 25: PIN DEFINITION OF SPI1 INTERFACE ......................................................................................... 68
TABLE 26: PIN DEFINITION OF SPI2 INTERFACE (MULTIPLEXED FROM UART1) .................................... 68
TABLE 27: PIN DEFINITION OF SPI3 INTERFACE (MULTIPLEXED FROM UART2) .................................... 68
TABLE 28: PARAMETERS OF SPI INTERFACE TIMING ................................................................................ 69
TABLE 29: PIN DEFINITION OF SGMII INTERFACE ...................................................................................... 70
TABLE 30: PIN DEFINITION OF WIRELESS CONNECTIVITY INTERFACES ................................................ 72
TABLE 31: PIN DEFINITION OF ADC INTERFACES ....................................................................................... 76
TABLE 32: CHARACTERISTIC OF ADC INTERFACES ................................................................................... 76
TABLE 33: PIN DEFINITION OF THE NETWORK STATUS INDICATOR (NET_STATUS) .............................. 77
TABLE 34: WORKING STATE OF THE NETWORK STATUS INDICATOR (NET_STATUS) ........................... 77
TABLE 35: PIN DEFINITION OF STATUS ........................................................................................................ 78
TABLE 36: PIN DEFINITION OF USB_BOOT INTERFACE ............................................................................. 79
TABLE 37: AG35-CE GNSS PERFORMANCE ................................................................................................. 80
TABLE 38: AG35-E GNSS PERFORMANCE .................................................................................................... 81
TABLE 39: AG35-NA GNSS PERFORMANCE ................................................................................................. 81
TABLE 40: AG35-LA GNSS PERFORMANCE .................................................................................................. 82
TABLE 41: AG35-J GNSS PERFORMANCE .................................................................................................... 82