Product Info

Automotive Module Series
AG35 Hardware Design
AG35_Hardware_Design 66 / 129
Module
WLAN_SLP_CLK
PM_ENABLE
DCDC/LDO
32KHZ_IN
AF20
VDD_3V3
POWER
SDC1_DATA3
SDC1_DATA2
SDC1_DATA1
SDC1_DATA0
SDC1_CLK
SDC1_CMD
WLAN_EN
SDIO_D3
SDIO_D2
SDIO_D1
SDIO_D0
SDIO_CLK
SDIO_CMD
WLAN_EN
WLAN
BT_EN
UART2_RTS
UART2_CTS
UART2_TXD
UART2_RXD
PCM_1A_IN
PCM_1A_OUT
PCM_1A_SYNC
PCM_1A_CLK
BT_EN*
BT_UART_RTS
BT_UART_CTS
BT_UART_RXD
BT_UART_TXD
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
Bluetooth
(Under Development)
VDD_EXT VIO
COEX_UART_TX
COEX_UART_RX
LTE_UART_TXD
LTE_UART_RXD
WLAN_WAKE
15~24R
Close to module
NM-0R
15K
10K
COEX
Figure 29: Reference Circuit for Connection with AF20 Module
3.16.1. WLAN Interface
AG35 provides a low power SDIO 3.0 interface and a control interface for WLAN design.
The WLAN interface (SDIO interface) supports the following modes:
 Single data rate (SDR) mode (up to 208MHz)
 Double data rate (DDR) mode (up to 50MHz)
As SDIO signals are very high-speed signals, in order to ensure the SDIO interface design corresponds
with the SDIO 3.0 specification, please comply with the following principles:
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal