Product Info

LTE Module Series
EC25 Hardware Design
EC25_Hardware_Design 54 / 112
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design.
Figure 20: Reference Circuit with Translator Chip
Please visit http://www.ti.com
for more information.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module’s input and output circuit
designs, but please pay attention to the direction of connection.
Parameter Min. Max. Unit
V
IL
-0.3 0.6 V
V
IH
1.2 2.0 V
V
OL
0 0.45 V
V
OH
1.35 1.8 V