Product Info

LTE Module Series
EC25 Hardware Design
EC25_Hardware_Design 60 / 112
 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data trace
is 50Ω (±10%).
 Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 15pF.
 It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 27mm, so the
exterior total trace length should be less than 23mm.
3.14. ADC Interfaces
The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 command can be
used to read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage
value on ADC1 pin. For more details about these AT commands, please refer to document [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
Table 16: Pin Definition of ADC Interfaces
The following table describes the characteristic of ADC function.
Table 17: Characteristic of ADC
Pin Name Pin No. Description
ADC0 45 General purpose analog to digital converter
ADC1 44 General purpose analog to digital converter
Parameter Min. Typ. Max. Unit
ADC0 Voltage Range 0.3 VBAT_BB V
ADC1 Voltage Range 0.3 VBAT_BB V
ADC Resolution 15 Bits