Product Info

ManualsBrandsQuectel ManualsElectronicsLTE-A Cat 12 LGA Module

EG12 Hardware Design

LTE-A Module Series

Rev. EG12_Hardware_Design_V1.0

Date: 2019-06-06

Status: Released

www.quectel.com

Summary of content (103 pages)

PAGE 1
EG12 Hardware Design LTE-A Module Series Rev. EG12_Hardware_Design_V1.0 Date: 2019-06-06 Status: Released www.quectel.
PAGE 2
LTE-A Module Series EG12 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
PAGE 3
LTE-A Module Series EG12 Hardware Design About the Document History Revision 1.
PAGE 4
LTE-A Module Series EG12 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index .....................................................................................................................................
PAGE 5
LTE-A Module Series EG12 Hardware Design 3.11.4. UART Application ........................................................................................................... 49 3.12. SPI Interface ............................................................................................................................ 51 3.13. PCM and I2C Interfaces .......................................................................................................... 52 3.14. ADC Interfaces ..........................
PAGE 6
LTE-A Module Series EG12 Hardware Design 6.8. Thermal Consideration ............................................................................................................ 86 7 Mechanical Dimensions .................................................................................................................... 89 7.1. Mechanical Dimensions of the Module.................................................................................... 89 7.2. Recommended Footprint .............................
PAGE 7
LTE-A Module Series EG12 Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF EG12 SERIES MODULE ....................................................................... 12 TABLE 2: KEY FEATURES OF EG12............................................................................................................... 14 TABLE 3: I/O PARAMETERS DEFINITION ...................................................................................................... 20 TABLE 4: PIN DESCRIPTION ..........................
PAGE 8
LTE-A Module Series EG12 Hardware Design TABLE 42: EG12-EA CURRENT CONSUMPTION .......................................................................................... 80 TABLE 43: RF OUTPUT POWER ..................................................................................................................... 84 TABLE 44: EG12-GT CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 85 TABLE 45: EG12-EA CONDUCTED RF RECEIVING SENSITIVITY ..................
PAGE 9
LTE-A Module Series EG12 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 19 FIGURE 3: DRX RUN TIME AND CURRENT CONSUMPTION IN SLEEP MODE ......................................... 32 FIGURE 4: SLEEP MODE APPLICATION VIA UART INTERFACES ..............
PAGE 10
LTE-A Module Series EG12 Hardware Design ................................................................................................................................................................... 74 FIGURE 39: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 76 FIGURE 40: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 76 FIGURE 41: SPACE FACTOR OF MATING PLUGS (UNIT: MM) ..............
PAGE 11
LTE-A Module Series EG12 Hardware Design 1 Introduction This document defines the EG12 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details, as well as other related information of EG12 module. Associated with application note and user guide, customers can use EG12 module to design and set up mobile applications easily.
PAGE 12
LTE-A Module Series EG12 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating EG12 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
PAGE 13
LTE-A Module Series EG12 Hardware Design 2 Product Concept 2.1. General Description EG12 is a series LTE-FDD/LTE-TDD/WCDMA wireless communication module with receive diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. EG12 supports embedded operating systems such as Windows, Linux and Android. It also provides GNSS 1) and voice functionality 2) to meet customers’ specific application demands.
PAGE 14
LTE-A Module Series EG12 Hardware Design B38+B38; B40+B40; B41+B41 B2+B4+B5/B13/B71; B2+B5+B66; B2+B12+B30; B2+B13+B66; B2+B7+B12/B66; B4+B30+B5/B12/B29; B4+B7+B12; B30+B66+B5/B12/B29; B2+B2+B5/B12/B13/ B29/B66; B5+B5+B2/B30/B66; B7+B7+B2/B4/B5; B66+B66+B2/B5/B13/B66; B41+B41+B25/B26/B41; 3×CA (DL) B42+B42+B42; B48+B48+B48 B1+B3+B3/B5/B7/B8/ B20/B28/B38/B41; B1+B40+B40; B1+B41+B41; B1+B7+B20; B3+B3+B7/B20/B28; B3+B7+B7/B8/B20/B28; B3+B40+B40; B3+B41+B41; B7+B7+B20/B28; B40+B40+B40; B41+B41+B41 WCDMA (w
PAGE 15
LTE-A Module Series EG12 Hardware Design 2.2. Key Features The following table describes the detailed features of EG12. Table 2: Key Features of EG12 Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.
PAGE 16
LTE-A Module Series EG12 Hardware Design Support long frame synchronization and short frame synchronization Support master and slave modes, but must be the master in long frame synchronization USB Interface UART Interfaces Comply with USB 3.0 and 2.0 specifications, with maximum transmission rates up to 5Gbps on USB 3.0 and 480Mbps on USB 2.
PAGE 17
LTE-A Module Series EG12 Hardware Design NOTES 1. 2. 3. "*" means under development. 1) Within operating temperature range, the module is 3GPP compliant. 2) Within extended temperature range, proper mounting, heating sinks and active cooling may be required to make certain functions of the module such as voice, SMS, data transmission, emergency call to be realized. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances.
PAGE 18
LTE-A Module Series EG12 Hardware Design 2.4. Evaluation Board In order to help customers develop applications with EG12, Quectel supplies an evaluation board (EVB), USB to RS-232 converter cable, earphone, antenna, and other peripherals to control or test the module. For more details, please refer to document [1].
PAGE 19
LTE-A Module Series EG12 Hardware Design 3 Application Interfaces 3.1. General Description EG12 is designed with 299 LGA pins that can be connected to cellular application platform.
PAGE 20
GND RESERVED 298 89 90 92 91 93 94 95 196 198 197 98 200 199 96 99 97 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ANT_MIMO1 101 100 103 102 104 202 201 105 107 106 203 109 204 205 108 110 111 113 112 206 114 207 209 ANT_MAIN ANT_MIMO2 RESERVED 115 116 118 117 119 120 210 208 RESERVED ANT_GNSS RESERVED RESERVED 211 212 122 121 123 124 125 127 133 85 135 83 215 216 217 218 219 220 221 222 80 79 140 78 141 224 225 226 227 22
PAGE 21
LTE-A Module Series EG12 Hardware Design NOTES 1. 2. Keep all RESERVED pins and unused pins unconnected. GND pins 215~299 should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition and description of EG12.
PAGE 22
LTE-A Module Series EG12 Hardware Design If an SD card is used, connect VDD_P2 to SD_VDD. If an eMMC* is used or SDIO interface is unused, connect VDD_P2 to VDD_EXT. SD card power supply VDD_P2 135 PI VDD_EXT 168 PO Provide 1.8V for external circuit. Vnorm=1.8V IOmax=50mA VDD_RF 162 PO Provide 2.85V for external RF circuit. Vnorm=2.
PAGE 23
LTE-A Module Series EG12 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open. NET_MODE 147 DO Indicate the module’s network registration mode NET_ STATUS 170 DO Indicate the module’s network activity status VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open. DO Indicate the module’s operation status VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open.
PAGE 24
LTE-A Module Series EG12 Hardware Design VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM: VILmax=0.57V VIHmin=2.0V VOLmax=0.4V VOHmin=2.3V For 1.8V (U)SIM: Vmax=1.9V Vmin=1.7V USIM2_VDD USIM2_DAT A USIM2_DET USIM2_RST USIM2_CLK 74 77 78 79 80 PO IO DI DO DO Power supply for (U)SIM2 card Data signal of (U)SIM2 card (U)SIM2 card insertion detection Reset signal of (U)SIM2 card Clock signal of (U)SIM2 card For 3.0V (U)SIM: Vmax=3.05V Vmin=2.75V IOmax=50mA For 1.8V (U)SIM: VILmax=0.36V VIHmin=1.
PAGE 25
LTE-A Module Series EG12 Hardware Design VOHmin=2.3V USB Interface Pin Name USB_VBUS USB_DM USB_DP USB_SS_ TX_M USB_SS_ TX_P USB_SS_ RX_P USB_SS_ RX_M Pin No. 32 33 34 37 38 40 41 I/O Description DC Characteristics PI USB connection detection Vmax=5.25V Vmin=3.3V Vnorm=5.0V IO USB 2.0 differential data bus - minus IO USB 2.0 differential data bus - plus AO USB 3.0 super speed transmission minus AO USB 3.0 super speed transmission - plus AI USB 3.
PAGE 26
LTE-A Module Series EG12 Hardware Design SD_DATA0 49 IO SDIO data signal (bit 0) For 1.8V SD card: VOLmax=0.45V VOHmin=1.4V VILmin=-0.3V VILmax=0.58V VIHmin=1.3V VIHmax=2.0V For 3.0V SD card: VOLmax=0.35V VOHmin=2.15V VILmin=-0.3V VILmax=0.7V VIHmin=1.8V VIHmax=3.15V If unused, keep it open. SD_DATA1 50 IO SDIO data signal (bit 1) If unused, keep it open. SD_DATA2 47 IO SDIO data signal (bit 2) If unused, keep it open. SD_DATA3 48 IO SDIO data signal (bit 3) If unused, keep it open.
PAGE 27
LTE-A Module Series EG12 Hardware Design DCD TXD RI DTR 59 60 61 62 Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Ring indication VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DI Data terminal ready, sleep mode control VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Pulled up by default.
PAGE 28
LTE-A Module Series EG12 Hardware Design BT UART interface pin by default. Can be multiplexed into SPI_CLK. BT_RXD BT_RTS 165 166 DI Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. BT UART interface pin by default. Can be multiplexed into SPI_MISO. 1.8V power domain. If unused, keep it open. BT UART interface pin by default. Can be multiplexed into SPI_CS. Comment DI Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.
PAGE 29
LTE-A Module Series EG12 Hardware Design open. PCM_OUT I2S_MCLK 68 152 DO PCM data output DO Clock output I/O Description IO Support all band main antenna interface AI Support all band RXD antenna interface AI Support all band 4x4 MIMO antenna interface VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Provide a digital clock output for an external audio codec. If unused, keep it open. Antenna Interfaces Pin Name ANT_MAIN ANT_DIV ANT_ MIMO1 Pin No.
PAGE 30
LTE-A Module Series EG12 Hardware Design If unused, keep it open. WAKE_ON_ WIRELESS 160 DI Wake up the host (EG12) by an external Wi-Fi module VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Active low. If unused, keep it open. WLAN_SLP_ CLK 169 DO WLAN sleep clock VOLmax=0.45V VOHmin=1.35V If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 173 AI General purpose analog to digital converter interface Voltage range: 0V to 1.
PAGE 31
LTE-A Module Series EG12 Hardware Design PCIE_WAKE_ 190 N VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V In slave mode, it is an input signal. If unused, keep it open. In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. IO PCIe wake up VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VIHmax=2.0V Description DC Characteristics Comment General purpose input/output port VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.
PAGE 32
LTE-A Module Series EG12 Hardware Design Pin Name USB_BOOT SLEEP_IND WAKEUP_IN W_DISABLE # Pin No. 140 144 150 151 I/O Description DC Characteristics Comment DI Force the module to enter into emergency download mode VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Active high If unused, keep it open. Sleep indication VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
PAGE 33
LTE-A Module Series EG12 Hardware Design Table 5: Overview of Operating Modes Mode Details Normal Operation mode Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode AT+CFUN=0 command can set the module to a minimum functionality mode without removing the power supply.
PAGE 34
LTE-A Module Series EG12 Hardware Design The following section describes power saving procedure of EG12. 3.5.1.1. UART Application If the host communicates with the module via UART interfaces, the following preconditions can let the module enter into sleep mode.   Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable sleep mode. The following figure shows the connection between the module and the host.
PAGE 35
LTE-A Module Series EG12 Hardware Design Host Module USB_VBUS USB Interface GND VDD USB Interface GND Figure 5: Sleep Mode Application with USB Remote Wakeup   Sending data to EG12 through USB will wake up the module. When EG12 has a URC to report, the module will send remote wake-up signals via USB bus to wake up the host. 3.5.1.3.
PAGE 36
LTE-A Module Series EG12 Hardware Design  When EG12 has a URC to report, RI signal will wake up the host. 3.5.1.4. USB Application without USB Suspend Function If the host does not support USB suspend function, USB_VBUS should be disconnected with an external control circuit to let the module enter into sleep mode.    Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable the sleep mode. Disconnect USB_VBUS.
PAGE 37
LTE-A Module Series EG12 Hardware Design Table 6: RF Function Status W_DISABLE# High Level Low Level AT Commands RF Function Module Operation AT+CFUN=1 RF Enabled Normal mode AT+CFUN=0 AT+CFUN=4 RF Disabled AT+CFUN=0: Minimum functionality mode AT+CFUN=4: Airplane mode AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 RF Disabled Airplane mode NOTES 1. The W_DISABLE# control function is disabled in firmware by default.
PAGE 38
LTE-A Module Series EG12 Hardware Design 92~94, 96~100, 102~106, 108~112, 114~118, 120~126, 128~133, 141, 142, 148, 153, 154, 157, 158, 167, 174, 177, 178, 181, 184, 187, 191, 196, 202~208, 214~299 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V. Please make sure the input voltage will never drop below 3.3V. The following figure shows the voltage drop during Tx power in 3G and 4G networks. Burst Transmission Burst Transmission VCC Min. 3.
PAGE 39
LTE-A Module Series EG12 Hardware Design VBAT VBAT_RF VBAT_BB + D1 5.1V C2 C3 100nF 33pF C1 100uF C5 + C6 + C7 C8 C9 10pF 100 uF 100uF 100nF 33pF 10pF C4 Module Figure 9: Star Structure of the Power Supply 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply of EG12 should be able to provide sufficient current up to 2A at least.
PAGE 40
LTE-A Module Series EG12 Hardware Design NOTE In order to avoid damaging internal flash, please do not switch off the power supply when the module works normally. Only after the module is shut down by PWRKEY or AT command, the power supply can be cut off. 3.6.4. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. 3.7. Turn on and off Scenarios 3.7.1.
PAGE 41
LTE-A Module Series EG12 Hardware Design Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from fingers. Therefore, it is necessary to place a TVS component nearby the button for ESD protection. A reference circuit is shown in the following figure: S1 PWRKEY TVS Close to S1 Figure 12: Turn on the Module Using a Button The turn-on scenario is illustrated in the following figure. NOTE VBAT ≥500ms VIH≥1.3V PWRKEY VIL≤0.
PAGE 42
LTE-A Module Series EG12 Hardware Design 3.7.2. Turn off the Module The following two methods can be used to turn off the module: using PWRKEY or AT+QPOWD command. 3.7.2.1. Turn off the Module Using PWRKEY Driving PWRKEY to a low level voltage for at least 800ms, the module will execute power-down procedure after the PWRKEY is released. The turn-off scenario is illustrated in the following figure.
PAGE 43
LTE-A Module Series EG12 Hardware Design 3.8. Reset the Module The module can be reset by driving RESET_N to a low level voltage for 250ms~600ms and then releasing it. Table 9: RESET_N Pin Description Pin Name RESET_N Pin No. 1 Description DC Characteristics Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Comment An open drain/collector driver or button can be used to control the RESET_N. A reference circuit is shown as below. RESET_N 250ms~600ms 4.
PAGE 44
LTE-A Module Series EG12 Hardware Design The reset scenario is illustrated in the following figure. VBAT ≤600ms ≥250ms VIH≥1.3V RESET_N VIL≤0.5V Module Status Running Resetting Restart Figure 17: Timing of Resetting the Module NOTES 1. 2. RESET_N can only be used when turning off the module failed either by AT+QPOWD command or PWRKEY. Please ensure that there is no large capacitance on PWRKEY and RESET_N. 3.9. (U)SIM Interfaces EG12 provides two (U)SIM interfaces.
PAGE 45
LTE-A Module Series EG12 Hardware Design USIM1_DATA 29 IO Data signal of (U)SIM1 card USIM2_VDD 74 PO Power supply for (U)SIM2 card Either 1.8V or 3.0V is supported by the module automatically. If (U)SIM2 interface is unused, keep it open. USIM2_ DATA 77 IO Data signal of (U)SIM2 card If (U)SIM2 interface is unused, keep it open. USIM2_DET 78 DI (U)SIM2 card insertion detection If (U)SIM2 interface is unused, keep it open.
PAGE 46
LTE-A Module Series EG12 Hardware Design USIM_VDD 15K 100nF Module USIM_VDD USIM_RST USIM_CLK USIM_DATA (U)SIM Card Connector VCC RST CLK 22R GND VPP IO 22R 22R NM NM NM GND Figure 19: Reference Circuit of a (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in the (U)SIM circuit design:       Keep placement of the (U)SIM card connector to the module as close as p
PAGE 47
LTE-A Module Series EG12 Hardware Design Table 11: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS 32 PI Used for detecting the USB connection Typical 5.0V USB_DP 34 IO USB 2.0 differential data bus - plus USB_DM 33 IO USB 2.0 differential data bus - minus USB_SS_ TX_M 37 AO USB 3.0 super-speed transmission minus USB_SS_ TX_P 38 AO USB 3.0 super-speed transmission plus USB_SS_ RX_P 40 AI USB 3.
PAGE 48
LTE-A Module Series EG12 Hardware Design Test Points Minimize these stubs Module VDD R3 NM_0R R4 NM_0R ESD Array USB_VBUS USB_DM USB_DP 100nF USB_SS_TX_P Host R1 0R USB_DM R2 0R USB_DP Close to Module USB_SS_RX_P C1 100nF USB_SS_RX_M USB_SS_TX_M C2 USB_SS_RX_P USB_SS_RX_M 100nF C3 100nF C4 USB_SS_TX_P USB_SS_TX_M USB_ID GPIO GND GND Figure 20: Reference Circuit of USB Application In order to ensure the signal integrity of USB data lines, C1, and C2 have been already installed
PAGE 49
LTE-A Module Series EG12 Hardware Design  2.0, and less than 0.4pF for USB 3.0. If possible, reserve a 0Ω resistor on USB_DP and USB_DM lines respectively. NOTE “*” means under development. 3.11. UART Interfaces The module provides three UART interfaces: main UART interface, debug UART interface, and BT UART interface.
PAGE 50
LTE-A Module Series EG12 Hardware Design RI 61 DO Ring indication 1.8V power domain DTR 62 DI Data terminal ready, sleep mode control 1.8V power domain 3.11.2. Debug UART Interface The following table shows the Debug UART interface pin definition. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 136 DI Receive data 1.8V power domain DBG_TXD 137 DO Transmit data 1.8V power domain 3.11.3.
PAGE 51
LTE-A Module Series EG12 Hardware Design Table 15: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V VDD_EXT VCCA 0.1uF 0.
PAGE 52
LTE-A Module Series EG12 Hardware Design VDD_EXT MCU/ARM 4.7K VDD_EXT 1nF Module 10K RXD TXD RXD TXD 10K VCC_MCU 1nF 4.7K VDD_EXT RTS CTS GPIO EINT GPIO GND RTS CTS DTR RI DCD GND Figure 22: Level Translation Reference Circuit with MOSFETs NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12. SPI Interface EG12 provides one SPI interface multiplexed from BT UART interface.
PAGE 53
LTE-A Module Series EG12 Hardware Design T t(ch) t(cl) SPI_CS_N 1 SPI_CLK 2 3 4 MSB SPI_MOSI t(mov) t(mis) t(mih) SPI_MISO Figure 23: Timing of SPI Interface The related parameters of SPI timing are shown in the following table. Table 17: Parameters of SPI Interface Timing Parameter Description Min. Typ. Max. Unit T SPI clock period 20.0 - - ns t(ch) SPI clock high level time 9.0 - - ns t(cl) SPI clock low level time 9.
PAGE 54
LTE-A Module Series EG12 Hardware Design In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, PCM interface supports 256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC, and also supports 4096kHz PCM_CLK at 16kHz PCM_SYNC. In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB.
PAGE 55
LTE-A Module Series EG12 Hardware Design The following table shows the pin definition of PCM interface and I2C interface, both of which can be applied on audio codec design. Table 18: Pin Definition of PCM interface and I2C Interface Pin Name Pin No. I/O Description Comment PCM_IN 66 DI PCM data input 1.8V power domain. If unused, keep it open. PCM_OUT 68 DO PCM data output 1.8V power domain. If unused, keep it open. IO PCM data frame synchronization signal 1.8V power domain.
PAGE 56
LTE-A Module Series EG12 Hardware Design PCM_CLK INP INN BCLK PCM_SYNC LRCK PCM_OUT DAC PCM_IN ADC I2C_SCL SCL I2C_SDA SDA BIAS MICBIAS Module 4.7K 4.7K LOUTP LOUTN Codec 1.8V Figure 26: Reference Circuit of PCM Application with Audio Codec NOTES 1. 2. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for PCM_CLK. EG12 works as a master device pertaining to I2C interface. 3.14.
PAGE 57
LTE-A Module Series EG12 Hardware Design Table 20: Characteristics of ADC Interfaces Parameter Min. ADC0 Voltage Range ADC1 Voltage Range Typ. Max. Unit 0 1.875 V 0 1.875 V ADC Resolution 15 bits NOTES 1. 2. 3. The input voltage of ADC should not exceed 1.875V. It is prohibited to supply any voltage to ADC pins when VBAT is removed. It is recommended to use resistor divider circuit for ADC application. 3.15.
PAGE 58
LTE-A Module Series EG12 Hardware Design Flicker quickly (125ms High/125ms Low) Data transfer ongoing Always High Voice calling A reference circuit is shown in the following figure. Module VBAT 2.2K Network Indicator 4.7K 47K Figure 27: Reference Circuit of the Network Indicator 3.16. STATUS The STATUS pin is set as the module status indicator. It outputs high level voltage when the module is turned on. The following table describes pin definition of STATUS.
PAGE 59
LTE-A Module Series EG12 Hardware Design VBAT Module 2.2K 4.7K STATUS 47K Figure 28: Reference Circuits of STATUS 3.17. Behavior of the RI AT+QCFG="risignaltype","physical" command can be executed to configure RI behavior. No matter on which port a URC is presented, the URC will trigger the behavior of RI pin. NOTE The URC can be output from UART port, USB AT port and USB modem port by executing AT+QURCCFG command. The default port is USB AT port. In addition, RI behavior can be configured flexibly.
PAGE 60
LTE-A Module Series EG12 Hardware Design 3.18. PCIe Interface* EG12 provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Specification, Revision 2.1 and supports 5Gbps per lane. The PCIe interface of EG12 is only used for data transmission.    PCI Express Specification Revision 2.
PAGE 61
LTE-A Module Series EG12 Hardware Design EG12 supports either Root Complex (RC) or Endpoint (EP) Mode through software configuration. 3.18.1. Root Complex Mode In this mode, the module is configured to act as a PCIe RC device. The following figure shows a reference circuit of PCIe RC mode.
PAGE 62
LTE-A Module Series EG12 Hardware Design Test Points Minimize these stubs NM_0R R3 Module NM_0R MCU R4 USB_DM USB_DP PCIE_RX_P PCIE_RX_M PCIE_TX_P C1 100nF PCIE_TX_M C2 100nF ESD Array R1 0R R2 0R USB_DM USB_DP C3 100nF C4 100nF PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M PCIE_REFCLK_P PCIE_REFCLK_P PCIE_REFCLK_M PCIE_REFCLK_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N GND PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N GND Figure 30: PCIe Interface Reference Circuit (EP Mode) In order to ensure th
PAGE 63
LTE-A Module Series EG12 Hardware Design 2. and software debugging can be over USB2.0/3.0 (USB2.0 is recommended). “*” means under development. 3.19. SDIO Interface* EG12 provides one SDIO interface which supports SD 3.0 protocol and eMMC*. The following table shows the pin definition. Table 26: Pin Definition of SDIO Interface Pin Name Pin No. I/O Description Comment 1.8V/3.0V configurable output. Cannot be used for SD card power supply.
PAGE 64
LTE-A Module Series EG12 Hardware Design Module VDD_EXT SD_VDD + R7 100K SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0 SD_CLK VDD_2V85 R8 100K R9 100K R10 100K R11 100K R12 470K VDD C10 100uF C9 100nF C8 33pF R1 0R C7 10pF CD/DAT3 R2 0R DAT2 R3 0R DAT1 R4 0R DAT0 R5 0R CLK R6 0R CMD SD_CMD SD_DET SD Card Connector C1 NM D1 C2 NM D2 C3 NM D3 C4 NM D4 C5 NM D5 D7 C6 NM D6 DETECTIVE VSS Figure 31: Reference Circuit of SD Card Application Please follow the principles below in the SD
PAGE 65
LTE-A Module Series EG12 Hardware Design 3.20. RFFE Interface* RFFE signals are used for external tuner control and should be routed to an appropriate antenna control circuitry. Table 27: Pin Definition of RFFE Interface Pin Name Pin No. I/O RFFE_CLK 71 DO RFFE_DATA 73 IO VDD_RF 162 PO Description RFFE serial interface used for external tuner control. Provide 2.85V for external RF circuit. Comment If unused, keep it open. If unused, keep it open. If unused, keep it open.
PAGE 66
LTE-A Module Series EG12 Hardware Design Module VDD_EXT Test point USB_BOOT TVS 10K Close to module Figure 32: Reference Circuit of USB_BOOT Interface 3.22. GPIOs The module provides 5 GPIOs for customers’ design. Table 29: Pin Definition of GPIOs Pin Name Pin No. I/O GPIO_1 138 IO If unused, keep it open. GPIO_2 139 IO If unused, keep it open. GPIO_3 159 IO GPIO_4 161 IO If unused, keep it open. GPIO_5 172 IO If unused, keep it open.
PAGE 67
LTE-A Module Series EG12 Hardware Design 4 GNSS Receiver 4.1. General Description EG12 includes a fully integrated global navigation satellite system solution that supports Gen9HT-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EG12 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, EG12 GNSS engine is switched off. It has to be switched on via AT command.
PAGE 68
LTE-A Module Series EG12 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous 3 s XTRA enabled 2 s Autonomous @open sky 1.5 m 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers’ design.     Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antennas.
PAGE 69
LTE-A Module Series EG12 Hardware Design 5 Antenna Interfaces EG12 provides a main antenna interface, an Rx-diversity antenna interface, two MIMO antenna interfaces, and a GNSS antenna interface. The impedance of antenna ports is 50Ω. 5.1. Main/Rx-diversity/MIMO Antenna Interfaces 5.1.1. Pin Definition The pin definition of main antenna interface, Rx-diversity and MIMO antenna interfaces are shown as below. Table 31: Pin Definition of the Main/Rx-diversity/MIMO Antenna Interfaces Pin Name Pin No.
PAGE 70
LTE-A Module Series EG12 Hardware Design Table 33: EG12-EA Operating Frequencies 3GPP Band Transmit Receive Unit WCDMA B1 1920~1980 2110~2170 MHz WCDMA B3 1710~1785 1805~1880 MHz WCDMA B5 824~849 869~894 MHz WCDMA B8 880~915 925~960 MHz LTE B1 1920~1979.9 2110~2169.9 MHz LTE B3 1710~1784.9 1805~1879.9 MHz LTE B5 824~848.9 869~893.9 MHz LTE B7 2500~2569.9 2620~2689.9 MHz LTE B8 880~914.9 925~959.9 MHz LTE B20 832~861.9 791~820.9 MHz LTE B28 703~747.9 758~802.
PAGE 71
LTE-A Module Series EG12 Hardware Design LTE B12 699~716 729~746 MHz LTE B13 777~787 746~756 MHz LTE B14 788~798 758~768 MHz LTE B17 704~716 734~746 MHz LTE B25 1850~1915 1930~1995 MHz LTE B26 814~849 859~894 MHz LTE B29 - 717~728 MHz LTE B30 2305~2315 2350~2360 MHz LTE B66 1710~1780 2110~2200 MHz LTE B71 617~652 663~698 MHz 5.1.3. Reference Design of RF Antenna Interfaces A reference design of ANT_MAIN, ANT_DIV, ANT_MIMO1 and ANT_MIMO2 interfaces is shown as below.
PAGE 72
LTE-A Module Series EG12 Hardware Design Module R1 0R ANT_MAIN C1 C2 NM NM R2 0R Diversity Antenna ANT_DIV C3 C4 NM NM R3 Main Antenna MIMO Antenna 0R ANT_MIMO1 C5 C6 NM NM R4 MIMO Antenna 0R ANT_MIMO2 C7 C8 NM NM Figure 33: Reference Circuit of RF Antenna Interfaces NOTE Keep a proper distance between the main antenna and the Rx-diversity antenna to improve the receiving sensitivity. 5.2. GNSS Antenna Interface 5.2.1.
PAGE 73
LTE-A Module Series EG12 Hardware Design 5.2.2. GNSS Frequency Table 36: GNSS Frequency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz Galileo 1575.42±2.046 MHz BeiDou 1561.098±2.046 MHz QZSS 1575.42 MHz 5.2.3. Reference Design of GNSS Antenna Interface A reference design of GNSS antenna is shown as below. VDD 0.1uF 10R Module GNSS Antenna 47nH 100pF 0R ANT_GNSS NM NM Figure 34: Reference Circuit of GNSS Antenna Interface NOTES 1. 2.
PAGE 74
LTE-A Module Series EG12 Hardware Design 5.3. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the clearance between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
PAGE 75
LTE-A Module Series EG12 Hardware Design Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 38: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω.
PAGE 76
LTE-A Module Series EG12 Hardware Design 5.4. Antenna Installation 5.4.1. Antenna Requirements The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna. Table 37: Antenna Requirements Type Requirements GNSS 1) Frequency range: 1559MHz~1609 MHz Polarization: RHCP or linear VSWR: <2 (Typ.) Passive antenna gain: >0dBi Active antenna noise figure: <1.
PAGE 77
LTE-A Module Series EG12 Hardware Design 5.4.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by Hirose. Figure 39: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT. Figure 40: Mechanicals of U.
PAGE 78
LTE-A Module Series EG12 Hardware Design The following figure describes the space factor of mating plugs. Figure 41: Space Factor of Mating Plugs (Unit: mm) For more details, please visit http://www.hirose.com.
PAGE 79
LTE-A Module Series EG12 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 38: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 1.0 A Peak Current of VBAT_RF 0 1.5 A Voltage at Digital Pins -0.3 2.3 V Voltage at ADC0 0 1.
PAGE 80
LTE-A Module Series EG12 Hardware Design minimum and maximum values. USB_VBUS USB connection detection 3.3 5.0 5.25 V 6.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 40: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range 1) -35 +25 +75 ºC Extended Operation Range 2) -40 +85 ºC Storage temperature range -40 +90 ºC NOTES 1. 2.
PAGE 81
LTE-A Module Series EG12 Hardware Design IVBAT IVBAT IVBAT IVBAT LTE-TDD PF=32 (USB disconnected) 2.54 mA LTE-TDD PF=64 (USB disconnected) 1.79 mA LTE-TDD PF=128 (USB disconnected) 1.41 mA LTE-TDD PF=256 (USB disconnected) 1.13 mA LTE-TDD PF=64 (USB Suspend) 2.10 mA LTE-TDD PF=64 (USB disconnected) 9.41 mA LTE-TDD PF=64 (USB active) 24.65 mA LTE-TDD B42 CH42590 @22.5dBm 350 mA LTE-TDD B43 CH44590 @22.5dBm 320 mA LTE-TDD B48 CH55990 @22.
PAGE 82
LTE-A Module Series EG12 Hardware Design IVBAT IVBAT IVBAT LTE-FDD PF=128 (USB disconnected) 2.11 mA LTE-FDD PF=256 (USB disconnected) 1.72 mA LTE-TDD PF=32 (USB disconnected) 4.39 mA LTE-TDD PF=64 (USB disconnected) 2.87 mA LTE-TDD PF=128 (USB disconnected) 2.21 mA LTE-TDD PF=256 (USB disconnected) 1.78 mA WCDMA PF=64 (USB Suspend) 2.74 mA LTE-FDD PF=64 (USB Suspend) 2.83 mA LTE-TDD PF=64 (USB Suspend) 2.96 mA WCDMA PF=64 (USB disconnected) 9.
PAGE 83
LTE-A Module Series EG12 Hardware Design IVBAT 2xCA data transfer EG12_Hardware_Design LTE-FDD B8 CH3625 @22.75dBm 583 mA LTE-FDD B20 CH6300 @22.6dBm 577 mA LTE-FDD B28 CH9435 @22.92dBm 576 mA LTE-TDD B38 CH38000 @22.58dBm 356 mA LTE-TDD B40 CH39150 @23.09dBm 353 mA LTE-TDD B41 CH40620 @22.79dBm 380 mA LTE-FDD+FDD B1+B1 @23.3dBm 627 mA LTE-FDD+FDD B1+ B3 @23.4dBm 565 mA LTE-FDD+FDD B1+ B5 @23.05dBm 556 mA LTE-FDD+FDD B1+ B7 @23.01dBm 570 mA LTE-FDD+FDD B1+ B8 @23.
PAGE 84
LTE-A Module Series EG12 Hardware Design IVBAT 3xCA data transfer EG12_Hardware_Design LTE-FDD+FDD B7+ B8 @23.1dBm 796 mA LTE-FDD+FDD B7+ B20 @23.08dBm 805 mA LTE-FDD+FDD B7+ B28 @23.2 dBm 807 mA LTE-FDD+TDD B20+ B38 @23.45dBm 643 mA LTE-FDD+TDD B20+ B40 @23.4dBm 640 mA LTE-TDD+TDD B38+ B38 @23.4dBm 398 mA LTE-TDD+TDD B40+ B40 @23.3dBm 376 mA LTE-TDD+TDD B41+ B41 @23.4dBm 398 mA LTE-FDD+FDD B1+ B3+B3 @22.92dBm 629 mA LTE-FDD+FDD B1+ B3+B5 @22.
PAGE 85
LTE-A Module Series EG12 Hardware Design IVBAT WCDMA voice call LTE-FDD+TDD B3+ B41+B41 @22.7dBm 729 mA LTE-FDD+FDD B7+ B7+B20 @22.77dBm 772 mA LTE-FDD+FDD B7+ B7+B28 @22.65dBm 775 mA LTE-TDD+TDD B40+ B40+B40 @23.01dBm 424 mA LTE-TDD+TDD B41+ B41+B41 @22.97dBm 525 mA WCDMA B1 CH10700 @22.94dBm 475 mA WCDMA B3 CH1338 @22.99dBm 524 mA WCDMA B5 CH4407 @23.19dBm 562 mA WCDMA B8 CH3012 @23.25dBm 577 mA 6.5. RF Output Power The following table shows the RF output power of EG12.
PAGE 86
LTE-A Module Series EG12 Hardware Design 6.6.1. EG12-GT Receiving Sensitivity Table 44: EG12-GT Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO1) 3GPP (SIMO) LTE-TDD B42 -98.4dBm -99.2dBm -102dBm -95dBm LTE-TDD B43 -98.5dBm TBD -101dBm -95dBm LTE-TDD B48 -98.2dBm -99.1dBm -104dBm -95dBm 6.6.2. EG12-EA Receiving Sensitivity Table 45: EG12-EA Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 1) 3GPP (SIMO) WCDMA B1 -111dBm -111dBm \ -106.
PAGE 87
LTE-A Module Series EG12 Hardware Design NOTE 1) SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which can improve Rx performance. 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is important to refer ESD handling precautions applying ESD sensitive components.
PAGE 88
LTE-A Module Series EG12 Hardware Design  or the opposite side of the PCB area where the module is mounted, or both of them. The heatsink should be designed with as many fins as possible to increase heat dissipation area. Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and module/PCB. The following shows two kinds of heatsink designs for reference and customers can choose one or both of them according to their application structure.
PAGE 89
LTE-A Module Series EG12 Hardware Design NOTES 1. 2. 3. Make sure that customers’ PCB design provides sufficient cooling solutions for the module: proper mounting, heatsinks, and active cooling may be required depending on the integrated application. In order to protect the components from damage, the thermal design should be maximally optimized to guarantee that the module’s internal temperature always maintains below 105°C.
PAGE 90
LTE-A Module Series EG12 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are ±0.05mm. 7.1.
PAGE 91
LTE-A Module Series EG12 Hardware Design Figure 45: Module Bottom Dimensions (Top View) EG12_Hardware_Design 90 / 100
PAGE 92
LTE-A Module Series EG12 Hardware Design 7.2. Recommended Footprint Figure 46: Recommended Footprint (Top View) NOTE For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB.
PAGE 93
LTE-A Module Series EG12 Hardware Design 7.3. Design Effect Drawings of the Module Figure 47: Top View of the Module Figure 48: Bottom View of the Module NOTE These are renderings of EG12. For authentic appearance, please refer to the module that you receive from Quectel.
PAGE 94
LTE-A Module Series EG12 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EG12 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10% RH. 3.
PAGE 95
LTE-A Module Series EG12 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module should be 0.13-0.15mm. For more details, please refer to document [4].
PAGE 96
LTE-A Module Series EG12 Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging EG12 is packaged in tape and reel carriers. Each reel is 10.56m long and contains 200 modules. The figures below show the packaging details, measured in mm.
PAGE 97
LTE-A Module Series EG12 Hardware Design Figure 51: Reel Specifications EG12_Hardware_Design 96 / 100
PAGE 98
LTE Module Sires EG12 Hardware Design 9 Appendix A References Table 48: Related Documents SN Document Name Remark [1] Quectel_UMTS<E_EVB_R2.0_User_Guide UMTS<E EVB R2.
PAGE 99
LTE Module Sires EG12 Hardware Design DFOTA Delta Firmware Upgrade Over The Air DL Downlink DRX Discontinuous Reception DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GNSS Global Navigation Satellite System GPS Global Positioning System HO-RXD Higher-order Receiver Diversity
PAGE 100
LTE Module Sires EG12 Hardware Design PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media Independent Interface SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing Tx Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System URC Un
PAGE 101
LTE Module Sires EG12 Hardware Design VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio EG12_Hardware_Design 100 / 100
PAGE 102
LTE Module Sires EG12 Hardware Design Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
PAGE 103
LTE Module Sires EG12 Hardware Design Radiation Exposure Statement: This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.