BG95-M3 Mini PCIe Hardware Design LPWA Module Series Rev. BG95-M3_Mini_PCIe_Hardware_Design_V1.0 Date: 2020-05-15 Status: Released www.quectel.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design About the Document Revision History Version 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ...............................................................................................................................
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. General Description .............................................................................................................. 38 Power Supply Requirements ................................................................................................. 38 Digital I/O Characteristics ...................................................................................................... 38 RF Characteristics .............
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table Index Table 1: Description of BG95-M3 Mini PCIe ............................................................................................ 10 Table 2: Key Features of BG95-M3 Mini PCIe .......................................................................................... 11 Table 3: Definition of I/O Parameters....................................................................................................... 15 Table 4: Pin Description ..
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure Index Figure 1: Functional Diagram .................................................................................................................. 13 Figure 2: Pin Assignment ........................................................................................................................ 15 Figure 3: Reference Design of Power Supply .........................................................................................
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 1 Introduction This document defines Quectel BG95-M3 Mini PCIe module, and describes its air interfaces and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand the interface specifications, electrical characteristics, mechanical specifications and other related information of the module. To facilitate application designs, it also includes some reference designs for customers’ reference.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design ❒ NB LTE Band14:≤12.272 dBi ❒NB LTE Band71:≤11.687 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 2 Product Concept 2.1. General Description BG95-M3 Mini PCIe is an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module with PCI Express Mini Card 1.2 standard interface. It provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS and voice 1) functionality to meet customers’ specific application demands.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 2.2. Key Features The following table describes the detailed features of BG95-M3 Mini PCIe module. Table 2: Key Features of BG95-M3 Mini PCIe Feature Details Function Interface PCI Express Mini Card 1.2 Standard Interface Power Supply Supply voltage: 3.0–3.6 V Typical supply voltage: 3.3 V Transmitting Power Class 5 (21 dBm +1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage: ME by default SMS (U)SIM Interface Support 1.8 V USIM/SIM card only UART Interfaces Audio Feature Support one digital audio interface: PCM interface for VoLTE and GSM CS voice only Baud rate can reach up to 230400 bps, 115200 bps by default Used for AT command communication and data transmission Compliant with USB 2.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 2.3. Functional Diagram The following figure shows the block diagram of BG95-M3 Mini PCIe. Figure 1: Functional Diagram NOTE The integrated (U)SIM card connector shares the same (U)SIM bus with the external (U)SIM card connector that is connected to Mini PCI Express (U)SIM interface. It does not support (U)SIM card detection function, and cannot be used simultaneously with the external (U)SIM card connector.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 3 Application Interfaces The physical connections and signal levels of BG95-M3 Mini PCIe comply with PCI Express Mini CEM specifications. This chapter mainly describes the definition and application of the following interfaces of BG95-M3 Mini PCIe: Power supply (U)SIM interface USB interface UART interface PCM and I2C interfaces* Control and indicator interfaces NOTE “*” means under development. 3.1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 2: Pin Assignment 3.2. Pin Description The following tables show the pin definition and description of BG95-M3 Mini PCIe.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table 4: Pin Description Pin No. Mini PCI Express Standard Name BG95-M3 Mini PCIe Pin Name I/O Description Comment 1 WAKE# WAKE# OC Used to wake up the host Active low 2 3.3 Vaux VCC_3V3 PI 3.0–3.6 V DC power supply, typically 3.3 V 3 COEX1 RESERVED Reserved 4 GND GND Mini card ground 5 COEX2 RESERVED Reserved 6 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 23 PERn0 UART_CTS DI UART clear to send 24 3.3 Vaux RESERVED 25 PERp0 UART_RTS 26 GND GND Mini card ground 27 GND GND Mini card ground 28 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 44 LED_WLAN# USIM_DET 45 RESERVED PCM_CLK 1) 46 LED_WPAN# RESERVED 47 RESERVED PCM_DOUT 1) 48 1.5V RESERVED 49 RESERVED PCM_DIN 1) 50 GND GND DI DO (U)SIM card insertion detection PCM clock signal 1.8 V power domain. For VoLTE and GSM CS voice only. Reserved DO PCM data output 1.8 V power domain. For VoLTE and GSM CS voice only. Reserved DI PCM data input 1.8 V power domain. For VoLTE and GSM CS voice only.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table 5: Overview of Operating Modes Mode Details Normal Operation Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode AT+CFUN=0 command can set the module to a minimum functionality mode without removing the power supply.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design MIC29302WU U1 VCC_3V3 LDO_IN 2 IN OUT 4 R2 R1 D1 C1 C2 TVS 470uF 100nF 51K 82K 1% R4 R3 R5 4.7K MCU_POWER _ON/OFF 470R C3 C4 470uF 100nF C5 C6 33pF 10pF 47K 1% R6 47K Figure 3: Reference Design of Power Supply 3.3. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Only 1.8 V (U)SIM card is supported. The following table shows the pin definition of (U)SIM interface.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 1.8V Module 51K USIM_VDD 100 nF 15K (U)SIM Card Connector GND USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA VCC RST 0R 0R CLK GND VPP IO 0R GND 33 pF 33 pF 33 pF GND GND Figure 4: Reference Design of (U)SIM Interface with 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design capacitor between USIM_VDD and GND should be not more than 1 μF and be placed close to the (U)SIM card connector. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. In order to offer good ESD protection, it is recommended to add a TVS diode with parasitic capacitance not exceeding 15 pF.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 6: Reference Design of USB Interface A common mode choke L1 is recommended to be added in series between the module and the MCU in order to suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R3 and R4) should be added in series between the module and the test points so as to facilitate debugging, and the resistors are not mounted by default.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 3.5. UART Interface The UART interface supports 9600, 19200, 38400, 57600, 115200 and 230400 bps baud rates. The default baud rate is 115200 bps. This interface can be used for AT command communication and data transmission. The following table shows the pin definition of the UART interface. Table 8: Pin Definition of UART Interface Pin Name Pin No. I/O Power Domain Description UART_RX 11 DI 3.3 V UART receive data UART_TX 13 DO 3.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 3.6. PCM and I2C Interfaces* BG95-M3 Mini PCIe provides one Pulse Code Modulation (PCM) digital interface and one I2C interface for VoLTE and GSM CS voice. The following table shows the pin definition of PCM and I2C interfaces that can be applied in audio codec design. Table 9: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Power Domain Description PCM_CLK 45 DO 1.8 V PCM clock signal PCM_DOUT 47 DO 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design NOTE PCM and I2C interfaces support VoLTE and GSM CS voice only. 3.7. Control and Indication Interfaces The following table shows the pin definition of control and indication interfaces. Table 10: Pin Definition of Control and Indication Interfaces Pin Name Pin No. I/O Power Domain Description RI 17 DO 3.3 V Used to wake up the host. DTR 31 DI 3.3 V Data terminal ready. W_DISABLE# 20 DI 3.3 V Airplane mode control.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 9: RI Behavior 3.7.2. W_DISABLE# W_DISABLE# enables/disables the RF function (excluding GNSS). It is pulled up by default, and driving it low makes the module enter airplane mode. The pin function is disabled by default, and AT+QCFG="airplanecontrol",1 can be used to enable this function.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design VCC_3V3 ≤ 3.8 s ≥2s VIH ≥ 2.3 V PERST# VIL ≤ 0.45 V Module Status Running Resetting Restart Figure 10: Reset Timing 3.7.4. LED_WWAN# LED_WWAN# indicates the network status of the module, and it absorbs a current up to 40 mA. According to the following circuit, in order to reduce the current of the LED, a resistor must be placed in series with the LED. The LED is powered on when LED_WWAN# is pulled low.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Always low Voice calling Table 14: Indications of Network Status (AT+QCFG="ledmode",1) Pin Status Description Low Level (Light on) Registered on network successfully High-impedance (Light off) No network coverage or not registered W_DISABLE# is at low level (airplane mode) AT+CFUN=0 or AT+CFUN=4 3.7.5.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 4 GNSS Receiver 4.1. General Description BG95-M3 Mini PCIe includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). The module supports standard NMEA 0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, the GNSS engine is switched off. It has to be switched on via AT command.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Accuracy (GNSS) @open sky XTRA enabled TBD s CEP-50 Autonomous @open sky <3 m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 5 Antenna Connection BG95-M3 Mini PCIe is mounted with two antenna connectors for external antenna connection: a main antenna connector and a GNSS antenna connector. The impedance of the antenna connectors is 50 Ω. Figure 13: Main and GNSS Antenna Connectors 5.1. Main Antenna Connector 5.1.1. Description of Main Antenna Connector The details of main antenna connector are shown below.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 5.1.2.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 5.2. GNSS Antenna Connector 5.2.1. Description of GNSS Antenna Connector The following tables show details of GNSS antenna connector. By default, the GNSS antenna connector supports active antennas with 3.3 V power supply design. It also supports passive antennas. Table 18: Description of GNSS Antenna Connector Connector I/O Description Comment GNSS AI GNSS antenna connector 50 Ω impedance 5.2.2.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 5.3. Antenna Requirements The following table shows the requirements on main and GNSS antennas. Table 20: Antenna Requirements Type Requirements GNSS Frequency range: 1559–1609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > 0 dBi Active antenna embedded LNA gain: < 17 dB Active antenna power supply: 3.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 14: Dimensions of Receptacles (Unit: mm) U.FL-LP mating plugs listed in the following figure can be used to match the receptacles. Figure 15: Mechanicals of U.FL-LP Mating Plugs The following figure describes the space factor of mated connectors.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 16: Space Factor of Mated Connectors (Unit: mm) For more details of the recommended mating plugs, please visit http://www.hirose.com.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. General Description This chapter mainly describes the following electrical and radio characteristics of BG95-M3 Mini PCIe: Power supply requirements Digital I/O characteristics RF characteristics ESD characteristics Current consumption 6.2. Power Supply Requirements The input voltage of BG95-M3 Mini PCIe is 3.3 V ±9% (3.0–3.6 V), as specified by PCI Express Mini CEM Specifications 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table 22: 3.3 V Digital I/O Characteristics Parameter Description Min. Max. Unit VIH Input High Voltage 0.7 × VCC_3V3 VCC_3V3 + 0.3 V VIL Input Low Voltage -0.3 0.3 × VCC_3V3 V VOH Output High Voltage VCC_3V3 - 0.5 VCC_3V3 V VOL Output Low Voltage 0 0.4 V Table 23: 1.8 V Digital I/O Characteristics Parameter Description Min. Max. Unit VIH Input High Voltage 1.2 2.0 V VIL Input Low Voltage -0.3 0.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design DCS1800/PCS1900 30 dBm ± 2 dB 0 dBm ± 5 dB GSM850/EGSM900 (8-PSK) 27 dBm ± 3 dB 5 dBm ± 5 dB DCS1800/PCS1900 (8-PSK) 26 dBm ± 3 dB 0 dBm ± 5 dB NOTES 1. 2. 1) 2) LTE-FDD B26 and B27 are supported by Cat M1 only. LTE-FDD B71 is supported by Cat NB2 only. Table19: Conducted RF Receiving Sensitivity Sensitivity (dBm) Band Primary Diversity Cat M1/3GPP Cat NB2 1)/3GPP LTE-FDD B1 -106/-102.3 -115/-107.5 LTE-FDD B2 -104.9/-100.3 -115/-107.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -104.3/-99.3 -116/-107.5 Sensitivity (dBm) Band Primary Diversity GSM/3GPP GSM850/EGSM900 -107/-102 Not Supported Supported DCS1800/PCS1900 -107/-102 NOTE 1) LTE Cat NB2 receiving sensitivity without repetitions. 6.5. ESD Characteristics The following table shows the ESD characteristics of the module.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table 21: Current Consumption of BG95-M3 Mini PCIe Description Idle Mode (USB connected) LTE Cat M1 data transfer (GNSS OFF) Conditions Average Max. Unit LTE Cat M1 DRX = 1.28 s 28 - mA LTE Cat NB1 DRX = 1.28 s 28 - mA LTE Cat M1 eDRX = 40.96 s @ PTW = 10.24 s, DRX = 2.56 s 27 - mA LTE Cat NB1 eDRX = 40.96 s @ PTW = 10.24 s, DRX = 2.56 s 27 - mA Band 1 @ 21.35 dBm 250 538 mA Band 2 @ 21.53 dBm 240 514 mA Band 3 @ 21.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design LTE Cat NB1 data transfer (GNSS OFF) GPRS data transfer (GNSS OFF) EDGE data transfer (GNSS OFF) Band 1 @ 21.14 dBm 204 484 mA Band 2 @ 21.11 dBm 371 496 mA Band 3 @ 21.65 dBm 206 493 mA Band 4 @ 21.51 dBm 203 481 mA Band 5 @ 21.33 dBm 400 533 mA Band 8 @ 21.13dBm 393 519 mA Band 12 @ 21.09 dBm 203 483 mA Band 13 @ 21.21 dBm 412 550 mA Band 18 @ 21.38 dBm 215 516 mA Band 19 @ 20.78 dBm 390 523 mA Band 20 @ 21.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Table 22: GNSS Current Consumption Parameter Description Searching (AT+CFUN=0) IVBAT (GNSS) Tracking (AT+CFUN=0) Conditions Typ.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 7 Dimensions and Packaging 7.1. General Description This chapter mainly describes mechanical dimensions as well as packaging specification of BG95-M3 Mini PCIe module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.2. Mechanical Dimensions of BG95-M3 Mini PCIe 30.00±0.15 24.20±0.2 8.35 6.39 Φ2.6±0.1 6.39 1.00±0.1 2.055±0.15 2.25±0.2 23.60±0.2 47.75±0.15 50.95±0.15 11.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 7.3. Standard Dimensions of Mini PCI Express The following figure shows the standard dimensions of Mini PCI Express. See document [1] for Detail A and Detail B. Figure 18: Standard Dimensions of Mini PCI Express BG95-M3 Mini PCIe adopts a standard Mini PCI Express connector which compiles with the directives and standards listed in document [1]. The following figure takes the Molex 679105700 as an example.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design Figure 19: Dimensions of the Mini PCI Express Connector (Molex 679105700) 7.4. Packaging Specification BG95-M3 Mini PCIe modules are packaged in a tray. Each tray contains 10 modules. The smallest package contains 100 modules.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 8 Appendix A References Table 23: Related Documents SN Document Name Remark [1] PCI Express Mini Card Electromechanical Specification Revision 1.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design GMSK Gaussian Minimum Shift Keying GNSS Global Navigation Satellite System GPS Global Positioning System GSM Global System for Mobile Communications kbps kilobits per second LED Light Emitting Diode LTE Long Term Evolution Mbps Million Bits Per Second MCU Micro Control Unit ME Mobile Equipment NMEA National Marine Electronics Association PCM Pulse Code Modulation PDA Personal Digital Assistant PDU Protocol Data Unit POS Point
LPWA Module Series BG95-M3 Mini PCIe Hardware Design USB Universal Serial Bus (U)SIM (Universal) Subscriber Identification Module BG95-M3_Mini_PCIe_Hardware_Design 50 / 53
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 9 Appendix B GPRS Coding Schemes Table 25: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl. USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate (kbps) 9.05 13.4 15.6 21.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 10 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 BG95-M3_Mini_PCIe_Hardware_Design 53 / 53
LPWA Module Series BG95-M3 Mini PCIe Hardware Design 11 Appendix D EDGE Modulation and Coding Schemes Table 27: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslots 4 Timeslots MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps MCS-2 GMSK B 11.2 kbps 22.4 kbps 44.8 kbps MCS-3 GMSK A 14.8 kbps 29.6 kbps 59.2 kbps MCS-4 GMSK C 17.6 kbps 35.2 kbps 70.4 kbps MCS-5 8-PSK B 22.4 kbps 44.8 kbps 89.6 kbps MCS-6 8-PSK A 29.6 kbps 59.
