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ManualsBrandsQuectel ManualsElectronicsSmart Module

SC600Y&SC600T

Hardware Design

Smart Module Series

Rev: SC600Y&SC600T_Hardware_Design_V1.0

Date: 2019-09-02

Status: Released

www.quectel.com

Summary of content (142 pages)

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SC600Y&SC600T Hardware Design Smart Module Series Rev: SC600Y&SC600T_Hardware_Design_V1.0 Date: 2019-09-02 Status: Released www.quectel.
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Smart Module Series SC600Y&SC600T Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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Smart Module Series SC600Y&SC600T Hardware Design About the Document History Revision Date Author Description 1.
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Smart Module Series SC600Y&SC600T Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ............................................................................................................................
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Smart Module Series SC600Y&SC600T Hardware Design 3.21.1. Design Considerations ................................................................................................... 75 3.21.2. Flashlight Interfaces ....................................................................................................... 77 3.22. Sensor Interfaces ...................................................................................................................... 78 3.23. Audio Interfaces ......................
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Smart Module Series SC600Y&SC600T Hardware Design 10 Appendix A References................................................................................................................... 118 删除的内容: About the Document 2 Contents 3 Table Index 6 Figure Index 8 1 Introduction 10 1.1. Safety Information 11 2 Product Concept 12 2.1. General Description 12 2.2. Key Features 15 2.3. Functional Diagram 19 2.4. Evaluation Board 20 3 Application Interfaces 21 3.1. General Description 21 3.2. Pin Assignment 22 3.
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Smart Module Series SC600Y&SC600T Hardware Design Table Index TABLE 1: SC600Y-EM/SC600T-EM FREQUENCY BANDS ........................................................................... 12 TABLE 2: SC600Y-NA/SC600T-NA FREQUENCY BANDS ............................................................................ 12 TABLE 3: SC600Y-JP/SC600T-JP FREQUENCY BANDS .............................................................................. 13 TABLE 4: SC600Y-WF/SC600T-WF FREQUENCY BANDS ............................
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Smart Module Series SC600Y&SC600T Hardware Design TABLE 50: RECOMMENDED THERMAL PROFILE PARAMETERS ............................................................. 115 TABLE 51: REEL PACKAGING...................................................................................................................... 117 TABLE 52: RELATED DOCUMENTS............................................................................................................. 118 TABLE 53: TERMS AND ABBREVIATIONS ........................
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删除的内容: 20 Smart Module Series SC600Y&SC600T Hardware Design 删除的内容: 22 删除的内容: 39 删除的内容: 40 Figure Index 删除的内容: 40 FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................. 18 删除的内容: 41 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................. 20 删除的内容: 42 FIGURE 3: VOLTAGE DROP SAMPLE .............................................................
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Smart Module Series SC600Y&SC600T Hardware Design FIGURE 38: REFERENCE CIRCUIT DESIGN FOR WI-FI/BT ANTENNA INTERFACE ............................... 100 FIGURE 39: REFERENCE CIRCUIT DESIGN FOR FM ANTENNA INTERFACE ........................................ 100 FIGURE 40: REFERENCE CIRCUIT DESIGN FOR GNSS PASSIVE ANTENNA ........................................ 101 删除的内容: 98 删除的内容: 99 FIGURE 41: REFERENCE CIRCUIT DESIGN FOR GNSS ACTIVE ANTENNA ..........................................
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Smart Module Series SC600Y&SC600T Hardware Design 1 Introduction This document defines the SC600Y/SC600T module and describes its air interfaces and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand module interface specifications, electrical and mechanical details as well as other related information of SC600Y/SC600T module.
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Smart Module Series SC600Y&SC600T Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating SC600Y/SC600T module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
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Smart Module Series SC600Y&SC600T Hardware Design 2 Product Concept 2.1. General Description SC600Y/SC600T is a series of Smart module based on Qualcomm platform and Android operating system, and provides industrial grade performance. Their general features are listed below:      Support short-range wireless communication via Wi-Fi 802.11a/b/g/n/ac and BT4.
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Smart Module Series SC600Y&SC600T Hardware Design GNSS GPS: 1575.42MHz±1.023MHz GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz±2.046MHz Table 3: SC600Y-JP/SC600T-JP Frequency Bands Type Frequency Bands Wi-Fi 802.11a/b/g/n/ac 2402MHz~2482MHz; 5180MHz~5825MHz* BT4.2 LE 2402MHz~2480MHz GNSS GPS: 1575.42MHz±1.023MHz GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz±2.046MHz 删除的内容: LTE-FDD ... [5] 删除的内容: LTE-FDD ...
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Smart Module Series SC600Y&SC600T Hardware Design 2.2. Key Features The following table describes the detailed features of SC600Y/SC600T module. Table 5: SC600Y/SC600T Key Features Features Details SC600Y Octa-core ARM Cortex-A53 64-bit CPU @1.8GHz (standard)  Two quad-core processors with 512KB L2 cache Application Processor SC600T Octa-core ARM Cortex-A53 64-bit CPU @2.
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Smart Module Series SC600Y&SC600T Hardware Design 2-lane + 1-lane) SC600Y Up to 21MP with dual ISP SC600T Up to 24MP with dual ISP Video Codec SC600Y Video encoding and decoding: up to 1080P @60fps Wi-Fi Video: encoding up to 1080P @30fps; decoding up to 1080P @60fps SC600T Video encoding and decoding: up to 4K @30fps, up to 1080P @60fps Wi-Fi Video: encoding up to 1080P @30fps; decoding up to 1080P @60fps Audio Interfaces Audio Input Three analog microphone inputs, integrating internal bias voltage Au
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Smart Module Series SC600Y&SC600T Hardware Design ADC Interfaces 2 general purpose ADC interfaces Support up to 15-bit sampling accuracy SPI Interfaces 2 SPI interfaces, only support master mode  One SPI interface used for peripheral device  One SPI interface used for sensor application, such as fingerprint sensor Charging Interface Used for battery voltage detection, fuel gauge, battery temperature detection Real Time Clock Supported Antenna Interfaces Main antenna, Rx-diversity antenna, GNSS a
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Smart Module Series SC600Y&SC600T Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of SC600Y/SC600T and illustrates the major functional parts.
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Smart Module Series SC600Y&SC600T Hardware Design Figure 1: Functional Diagram 2.4. Evaluation Board In order to help customers develop applications with SC600Y/SC600T conveniently, Quectel supplies the evaluation board, USB to RS232 converter cable, USB Type-C data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document [1].
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Smart Module Series SC600Y&SC600T Hardware Design 3 Application Interfaces 3.1. General Description SC600Y/SC600T is equipped with 323 pins that can be embedded into cellular application platform. The following chapters provide the detailed description of pins/interfaces listed below.
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Smart Module Series SC600Y&SC600T Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of SC600Y/SC600T module.
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Smart Module Series SC600Y&SC600T Hardware Design 3.3. Pin Description Table 6: I/O Parameters Definition Type Description AI Analog input AO Analog output DI Digital input DO Digital output IO Bidirectional OD Open drain PI Power input PO Power output The following tables show the SC600Y/SC600T’s pin definitions and electrical characteristics. Table 7: Pin Description Power Supply Pin Name VBAT Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design Vnorm=3.8V VRTC LDO5_1P8 LDO10_2P8 LDO6_1P8 LDO17_2P85 LDO23_1P2 16 9 11 10 12 15 current of 1A approximately. The value of capacitors placed on this pin should not exceed 120uF. PI/P O Power supply for internal RTC circuit VOmax=3.2V VI=2.0V~3.25V PO 1.8V output power supply Vnorm=1.8V IOmax=20mA Power supply for external GPIO’s pull up circuits and level shift circuit. Vnorm=2.8V IOmax=150mA Power supply for VDD of sensors and TPs.
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Smart Module Series SC600Y&SC600T Hardware Design LDO2_1P1 13 LDO22_2P8 14 GND 3, 4, 18, 20, 31, 34, 35, 40, 43, 47, 56, 62, 87, 98, 101, 112, 125, 128, 130, 133, 135, 148, 150, 159, 163, 170, 173, 176, 182, 193, 195, 219, 225, 243, 257~323 PO PO 1.1V output power supply 2.8V output power supply Vnorm=1.1V IOmax=1200mA Power supply for DVDD of rear camera. Add a 1.0uF~2.2uF bypass capacitor if used. If unused, keep this pin open. Vnorm=2.8V IOmax=150mA Power supply for AVDD of camera. Add a 1.
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Smart Module Series SC600Y&SC600T Hardware Design MIC2_P 46 AI Microphone input for headset (+) MIC3_P 169 AI Microphone input for channel 2 (+) EAR_P 53 AO Earpiece output (+) EAR_N 52 AO Earpiece output (-) SPK_P 55 AO Speaker output (+) SPK_N 54 AO Speaker output (-) HPH_R 51 AO Headphone right channel output HPH_REF 50 AI Headphone reference ground HPH_L 49 AO Headphone left channel output HS_DET 48 AI Headset insertion detection LINE_OUT_P 227 AO Audio line d
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Smart Module Series SC600Y&SC600T Hardware Design USB_SS_TX _P 174 AO USB 3.0 differential transmit data (+) USB_SS_TX _M 175 AO USB 3.
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Smart Module Series SC600Y&SC600T Hardware Design VOHmin= 0.8 × USIM1_VDD USIM1_VDD USIM2_DET 141 256 PO DI (U)SIM1 card power supply 1.8V (U)SIM: Vmax=1.90V Vmin=1.70V 2.95V (U)SIM: Vmax=3.04V Vmin=2.7V (U)SIM2 card hot-plug detection VILmax=0.63V VIHmin=1.17V USIM2_RST 207 DO (U)SIM2 card reset VOLmax=0.4V VOHmin= 0.8 × USIM2_VDD USIM2_CLK 208 DO (U)SIM2 card clock VOLmax=0.4V VOHmin= 0.8 × USIM2_VDD (U)SIM2 card data VILmax= 0.2 × USIM2_VDD VIHmin= 0.7 × USIM2_VDD VOLmax=0.
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Smart Module Series SC600Y&SC600T Hardware Design by default pins open. UART2_RXD 6 DI UART2 receive data. Used for debugging by default VILmax=0.63V VIHmin=1.17V UART4_TXD 7 DO UART4 transmit data VOLmax=0.45V VOHmin=1.35V UART4_RXD 8 DI UART4 receive data VILmax=0.63V VIHmin=1.17V UART5_RXD 198 DI UART5 receive data VILmax=0.63V VIHmin=1.17V UART5_TXD 199 DO UART5 transmit data VOLmax=0.45V VOHmin=1.35V UART5_RTS 245 DO UART5 request to send VOLmax=0.45V VOHmin=1.
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Smart Module Series SC600Y&SC600T Hardware Design SD_DATA1 67 VOLmax=0.45V VOHmin=1.4V IO 2.95V SD card: VILmax=0.73V VIHmin=1.84V VOLmax=0.37V VOHmin=2.2V SD_DATA2 66 IO SD_DATA3 65 IO SD_DET 64 DI SD card insertion detection VILmax=0.63V VIHmin=1.17V SD_LDO11 63 PO Power supply for SD card Vnorm=2.95V IOmax=800mA SD_LDO12 179 PO 1.8V/2.95V output Vnorm=1.8V/2.95V IOmax=50mA Power supply for SD card’s pull-up circuit. Active low. TP (Touch Panel) Interfaces Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design LCD_BL_A 21 PO Current output for LCD backlight LCD_BL_K1 22 AI Current sink for LCD backlight LCD_BL_K2 23 AI Current sink for LCD backlight LCD_BL_K3 24 AI Current sink for LCD backlight LCD_BL_K4 25 AI Current sink for LCD backlight PMU_MPP4 152 DO PWM output VOLmax=0.45V VOHmin=1.35V LCD0_RST 127 DO LCD0 reset VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. LCD0_TE 126 DI LCD0 tearing effect VILmax=0.
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Smart Module Series SC600Y&SC600T Hardware Design DSI0_LN3_P 123 AO LCD0 MIPI lane 3 data signal (+) DSI1_CLK_N 103 AO LCD1 MIPI clock signal (-) DSI1_CLK_P 102 AO LCD1 MIPI clock signal (+) DSI1_LN0_N 105 AO LCD1 MIPI lane 0 data signal (-) DSI1_LN0_P 104 AO LCD1 MIPI lane 0 data signal (+) DSI1_LN1_N 107 AO LCD1 MIPI lane 1 data signal (-) DSI1_LN1_P 106 AO LCD1 MIPI lane 1 data signal (+) DSI1_LN2_N 109 AO LCD1 MIPI lane 2 data signal (-) DSI1_LN2_P 108 AO LCD1 MIPI la
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Smart Module Series SC600Y&SC600T Hardware Design CSI0_LN3_N 97 AI MIPI lane 3 data signal of rear camera (-) CSI0_LN3_P 96 AI MIPI lane 3 data signal of rear camera (+) CSI1_CLK_N 184 AO MIPI clock signal of depth camera (-) CSI1_CLK_P 183 AO MIPI clock signal of depth camera (+) CSI1_LN0_N 186 AI MIPI lane 0 data signal of depth camera (-) CSI1_LN0_P 185 AI MIPI lane 0 data signal of depth camera (+) CSI1_LN1_N 188 AI MIPI lane 1 data signal of depth camera (-) CSI1_LN1_P 187
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Smart Module Series SC600Y&SC600T Hardware Design CSI2_LN2_P 83 AI MIPI lane 2 data signal of front camera (+) CSI2_LN3_N 86 AI MIPI lane 3 data signal of front camera (-) CSI2_LN3_P 85 AI MIPI lane 3 data signal of front camera (+) MCAM_MCLK 99 DO Master clock of rear camera VOLmax=0.45V VOHmin=1.35V 1.8V power domain. SCAM_MCLK 100 DO Master clock of front camera VOLmax=0.45V VOHmin=1.35V 1.8V power domain. MCAM_RST 74 DO Reset of rear camera VOLmax=0.45V VOHmin=1.35V 1.
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Smart Module Series SC600Y&SC600T Hardware Design PWRKEY 39 DI Turn on/off the module VILmax=0.63V VIHmin=1.17V Pull-up to 1.8V internally. Active low. VOL_UP 146 DI Volume up VILmax=0.63V VIHmin=1.17V If unused, keep this pin open. VOL_ DOWN 147 DI Volume down VILmax=0.63V VIHmin=1.17V If unused, keep this pin open. DC Characteristics Comment SENSOR_I2C Interface Pin Name Pin No. I/O Description SENSOR_I2C_ SCL 131 OD I2C clock for external sensors 1.8V power domain.
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Smart Module Series SC600Y&SC600T Hardware Design ANT_GNSS 134 AI GNSS antenna interface ANT_WIFI/BT 129 AI/ AO Wi-Fi/BT antenna interface ANT_FM 244 AI FM antenna interface Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design 178 IO General-purpose input/output Pin Name Pin No. I/O Description SPI_CS 58 DO SPI chip select Can be multiplexed into UART6_CTS. SPI_CLK 59 DO SPI clock Can be multiplexed into UART6_RTS. SPI_MOSI 60 DO SPI master-out slave-in Can be multiplexed into UART6_TXD. SPI_MISO 61 DI SPI master-in salve-out Can be multiplexed into UART6_RXD. FP_SPI_CS 203 DO SPI chip select Can be multiplexed into I2S_WS.
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Smart Module Series SC600Y&SC600T Hardware Design Pulled up to LDO5_1P8 during power-up will force the module to enter emergency download mode. 57 DI Force the module enter emergency download mode Pin Name Pin No. I/O Description BAT_ID 17 AI Battery type detection If unused, keep this pin open. AI Battery temperature measurement Internally pulled up. Externally connected to GND via a 47K NTC resistor. GNSS_LNA_EN 202 DO LNA enable control For test purpose only.
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Smart Module Series SC600Y&SC600T Hardware Design 3.4. Power Supply 3.4.1. Power Supply Pins SC600Y/SC600T provides 3 VBAT pins and 2 VPH_PWR pins. VBAT pins are dedicated for connection with an external power supply. VPH_PWR pins can supply power for peripherals, and it can provide a maximum continuous current of 1A approximately. The value of capacitors placed on this pin should not exceed 120uF. 3.4.2. Decrease Voltage Drop The power supply range of the module is from 3.55V to 4.
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Smart Module Series SC600Y&SC600T Hardware Design In addition, in order to get a stable power source, it is suggested to use a 0.5W TVS and place it as close to the VBAT pins as possible to increase voltage surge withstand capability. The following figure shows the structure of the power supply. Figure 4: Star Structure of Power Supply 3.4.3. Reference Design for Power Supply The power design for the module is very important, as the performance of module largely depends on the power source.
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Smart Module Series SC600Y&SC600T Hardware Design NOTES 1. 2. 3. It is recommended to switch off the power supply for module in abnormal state, and then switch on the power to restart the module. The module supports battery charging function by default. If the above power supply design is adopted, please make sure the charging function is disabled by software, or connect VBAT to Schottky diode in series to avoid the reverse current to the power supply chip.
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Smart Module Series SC600Y&SC600T Hardware Design Another way to control the PWRKEY is using a button directly. A TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module Using Keystroke The timing of turning on is illustrated in the following figure. VBA T(Typ.:3.8V) Note2 PWRKEY >1.6s 61.
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Smart Module Series SC600Y&SC600T Hardware Design NOTES 1. 2. The turn-on timing might be different from the above figure when the module powers on for the first time. Make sure that VBAT is stable before pulling down PWRKEY pin. The recommended time between them is no less than 30ms. PWRKEY cannot be pulled down all the time. 3.5.2. Turn off Module Pull down PWRKEY for at least 1s, and then choose to turn off the module when a prompt window comes up.
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Smart Module Series SC600Y&SC600T Hardware Design 3.6. VRTC Interface The RTC (Real Time Clock) can be powered by an external power source through VRTC when the module is powered down and there is no power supply for the VBAT. The external power source can be rechargeable battery (such as coil cells) according to application demands. The following reference circuit design when an external battery is utilized for powering RTC.
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Smart Module Series SC600Y&SC600T Hardware Design 3.7. Power Output SC600Y/SC600T supports output of regulated voltages for peripheral circuits. During application, it is recommended to use parallel capacitors (33pF and 10pF) in the circuit to suppress high frequency noise. Table 8: Power Description Pin Name Default Voltage (V) Drive Current (mA) Idle LDO5_1P8 1.8 20 Keep LDO6_1P8 1.8 300 / LDO10_2P8 2.8 150 / LDO17_2P85 2.85 300 / LDO2_1P1 1.1 1200 / LDO22_2P8 2.
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Smart Module Series SC600Y&SC600T Hardware Design 3.8. Battery Charge and Management SC600Y/SC600T supports a fully programmable switch-mode Li-ion battery charge function. It can charge single-cell Li-ion and Li-polymer batteries. The battery charger of SC600Y/SC600T supports trickle charging, pre-charge, constant current charging and constant voltage charging modes, which optimize the charging procedure for Li-ion and Li-polymer batteries.   Trickle charging: When the battery voltage is below 2.
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Smart Module Series SC600Y&SC600T Hardware Design SC600Y/SC600T supports battery temperature detection in the condition that the battery integrates a thermistor (47KΩ 1% NTC thermistor with B-constant of 4050KΩ by default; SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to BAT_THERM pin. If BAT_THERM pin is not connected, there will be malfunctions such as boot error, battery charging failure, battery level display error, etc.
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Smart Module Series SC600Y&SC600T Hardware Design 3.9. USB Interface SC600Y/SC600T provides one USB 3.0/2.0 compliant integrated Universal Serial Bus (USB) interface, which supports super speed (5Gbps) on USB 3.0, high speed (480Mbps) on USB 2.0, full speed (12Mbps) modes as well as USB OTG function. This USB interface is used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface.
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Smart Module Series SC600Y&SC600T Hardware Design USB_VBUS can be powered by a USB power or an adapter. It is used for USB connection detection and power supply input for battery charging. Its input voltage ranges from 4.0V to 10.0V, and the typical value is 5.0V. SC600Y/SC600T supports charging management for a single cell Li-ion battery, but varied charging parameters should be set for batteries with varied models or capacities. The maximum charging current is up to 3.0A.
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Smart Module Series SC600Y&SC600T Hardware Design The following is a reference design for USB Type-C interface: Module USB Type-C USB_ VBUS VUSB_ VBUS USB_DM DD+ USB_DP CC1 CC2 CC1 CC2 USB_SS_TX_P USB_SS_TX_M USB_SS_RX_P USB_SS_RX_M C2 A0+ B0+ C6 C3 A0- B0- C7 C4 A1+ B1+ C8 C5 A0- USB_SS_SEL B1- C9 C0+ C10 SEL C0- C11 VDD_3V USB_OPT R1 NM TX2+ TX2RX2+ RX2TX1+ TX1RX1+ RX1- VDD C1 4.
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Smart Module Series SC600Y&SC600T Hardware Design 172 USB_SS_RX_M 28.23 174 USB_SS_TX_P 19.58 175 USB_SS_TX_M 19.35 0.23 3.10. UART Interfaces The module provides the following four UART interfaces:     UART5: 4-wire UART interface, hardware flow control supported. UART6: 4-wire UART interface, hardware flow control supported, multiplexed from SPI interface. UART2: 2-wire UART interface, used for debugging. UART4: 2-wire UART interface.
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Smart Module Series SC600Y&SC600T Hardware Design Can be multiplexed into UART6_TXD. SPI_CS SPI_CLK 58 59 DI DO UART6 clear to send SPI interface pin by default. Can be multiplexed into UART6_CTS. UART6 request to send SPI interface pin by default. Can be multiplexed into UART6_RTS. UART5 is a 4-wire UART interface with 1.8V power domain. A level translator chip should be used if customers’ application is equipped with a 3.3V UART interface.
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Smart Module Series SC600Y&SC600T Hardware Design The following figure is an example of connection between SC600Y/SC600T and PC. A voltage level translator and a RS-232 level translator chip are recommended to be added between the module and PC, as shown below: Figure 15: RS232 Level Match Circuit (for UART5) NOTE UART2, UART4 and UART6 are similar to UART5. Please refer to UART5 reference circuit design for that of the UART2, UART4 and UART6. 3.11.
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Smart Module Series SC600Y&SC600T Hardware Design USIM1_RST 144 DO (U)SIM1 card reset USIM1_CLK 143 DO (U)SIM1 card clock USIM1_DATA 142 IO (U)SIM1 card data Pull up to USIM1_VDD with a 10KΩ resistor. USIM1_VDD 141 PO (U)SIM1 card power supply Either 1.8V or 2.95V (U)SIM card is supported. Active low. Require external pull-up to 1.8V. If unused, keep this pin open. Disabled by default and can be enabled through software configuration.
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Smart Module Series SC600Y&SC600T Hardware Design If there is no need to use USIM_DET, please keep it open. The following is a reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector. Figure 17: Reference Circuit for (U)SIM Interface with a 6-pin (U)SIM Card Connector In order to ensure good performance and avoid damage of (U)SIM cards, please follow the criteria below in (U)SIM circuit design:       Keep placement of (U)SIM card connector as close to the module as possible.
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Smart Module Series SC600Y&SC600T Hardware Design 3.12. SD Card Interface SC600Y/SC600T supports SD 3.0 specifications. The pin definition of the SD card interface is shown below. Table 14: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SD_LDO11 63 PO Power supply for SD card Vnorm=2.95V IOmax=800mA SD_LDO12 179 PO Power supply for SD card’s pull-up circuit 1.8V/2.95V output.
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Smart Module Series SC600Y&SC600T Hardware Design SD_LDO11 is a peripheral driver power supply for SD card. The maximum drive current is approximate 800mA. Because of the high drive current, it is recommended that the trace width is 0.5mm or above. In order to ensure the stability of drive power, a 4.7uF and a 33pF capacitor should be added in parallel near the SD card connector. CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines.
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Smart Module Series SC600Y&SC600T Hardware Design 3.13. GPIO Interfaces SC600Y/SC600T has abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed below. Table 16: Pin Definition of GPIO Interfaces Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design SPI_MOSI 60 GPIO_20 B-PD:nppukp SPI_MISO 61 GPIO_21 B-PD:nppukp SPI_CS 58 GPIO_22 B-PD:nppukp SPI_CLK 59 GPIO_23 B-PD:nppukp LCD0_TE 126 GPIO_24 B-PD:nppukp LCD1_TE 114 GPIO_25 B-PD:nppukp MCAM_MCLK 99 GPIO_26 B-PD:nppukp SCAM_MCLK 100 GPIO_27 B-PD:nppukp DCAM_MCLK 194 GPIO_28 B-PD:nppukp CAM_I2C_SDA 76 GPIO_29 B-PD:nppukp CAM_I2C_SCL 75 GPIO_30 B-PD:nppukp DCAM_I2C_SDA 197 GPIO_31 B-PD:nppukp DCAM_I2C_SCL 19
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Smart Module Series SC600Y&SC600T Hardware Design GPIO_89 232 GPIO_89 B-PD:nppukp GPIO_90 231 GPIO_90 B-PD:nppukp GPIO_96 230 GPIO_96 B-PD:nppukp GPIO_97 229 GPIO_97 B-PD:nppukp GPIO_98 177 GPIO_98 B-PD:nppukp GPIO_99 178 GPIO_99 B-PD:nppukp CAM4_MCLK 236 GPIO_128 B-PD:nppukp SCAM_RST 72 GPIO_129 B-PD:nppukp Wake up SCAM_PWDN 3) 71 GPIO_130 B-PD:nppukp Wake up DCAM_RST 180 GPIO_131 B-PD:nppukp Wake up DCAM_PWDN 3) 181 GPIO_132 B-PD:nppukp Wake up SD_DET 64
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Smart Module Series SC600Y&SC600T Hardware Design 3.14. I2C Interfaces SC600Y/SC600T provides five groups of I2C interfaces. As an open drain output, each I2C interface should be pulled up to 1.8V. The SENSOR_I2C interface supports only sensors of the aDSP architecture. CAM/DCAM_I2C bus is controlled by Linux Kernel code and supports connection to video output related devices.
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Smart Module Series SC600Y&SC600T Hardware Design 3.15. I2S Interface SC600Y/SC600T provides one I2S interface. The I2S interface is multiplexed from FP_SPI, with power domain of 1.8V . Table 18: Pin Definition of I2S Interface Pin Name Pin No I/O Description Comment FP_SPI_CS 203 DO SPI chip select SPI interface pin by default. Can be multiplexed into I2S_WS (I2S word select (L/R)). FP_SPI_CLK 250 DO SPI clock SPI interface pin by default. Can be multiplexed into I2S_SCK (I2S bit clock).
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Smart Module Series SC600Y&SC600T Hardware Design 3.16. SPI Interfaces SC600Y/SC600T provides two SPI interfaces which only support master mode. The two interfaces are typically applied for fingerprint identification. Table 19: Pin Definition of SPI Interfaces Pin Name Pin No I/O SPI_CS 58 DO SPI chip select Can be multiplexed into UART6_CST. SPI_CLK 59 DO SPI clock Can be multiplexed into UART6_RTS. SPI_MOSI 60 DO SPI master-out slave-in Can be multiplexed into UART6_TXD.
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Smart Module Series SC600Y&SC600T Hardware Design 3.17. ADC Interfaces SC600Y/SC600T provides two analog-to-digital converter (ADC) interfaces, and the pin definition is shown below. Table 20: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment PMI_ADC 153 AI General purpose ADC interface Maximum input voltage: 1.5V. PMU_MPP2 151 AI General purpose ADC interface Maximum input voltage: 1.7V. The resolution of the ADC is up to 15 bits.
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Smart Module Series SC600Y&SC600T Hardware Design 3.18. Vibrator Drive Interface The pin definition of vibrator drive interface is listed below. Table 21: Pin Definition of Vibrator Drive Interface Pin Name Pin No VIB_GND 160 VIB_DRV 161 I/O PO Description Comment Vibrator GND (-) Connected to the negative terminal of vibrator. Vibrator drive (+) Connected to the positive terminal of vibrator. The vibrator is driven by an exclusive circuit, and a reference circuit design is shown below.
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Smart Module Series SC600Y&SC600T Hardware Design 3.19. LCM Interfaces SC600Y/SC600T provides two LCM interfaces, and supports dual LCDs with WUXGA (1900×1200) display. These interfaces support high speed differential data transmission, with up to eight lanes. Table 22: Pin Definition of LCM Interfaces Pin Name Pin No. I/O Description LDO6_1P8 10 PO 1.8V output power supply LCM logic circuit and DSI LDO17_2P85 12 PO 2.
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Smart Module Series SC600Y&SC600T Hardware Design DSI0_LN1_P 119 AO LCD0 MIPI lane 1 data signal (+) DSI0_LN2_N 122 AO LCD0 MIPI lane 2 data signal (-) DSI0_LN2_P 121 AO LCD0 MIPI lane 2 data signal (+) DSI0_LN3_N 124 AO LCD0 MIPI lane 3 data signal (-) DSI0_LN3_P 123 AO LCD0 MIPI lane 3 data signal (+) DSI1_CLK_N 103 AO LCD1 MIPI clock signal (-) DSI1_CLK_P 102 AO LCD1 MIPI clock signal (+) DSI1_LN0_N 105 AO LCD1 MIPI lane 0 data signal (-) DSI1_LN0_P 104 AO LCD1 MIPI la
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Smart Module Series SC600Y&SC600T Hardware Design The following are the reference designs for LCM interfaces.
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Smart Module Series SC600Y&SC600T Hardware Design Figure 21: Reference Circuit Design for LCM1 Interface MIPI are high speed signal lines. It is recommended that common-mode filters should be added in series near the LCM connector, so as to improve protection against electromagnetic radiation interference.
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Smart Module Series SC600Y&SC600T Hardware Design   Power two strings of WLEDs (about 14 WLEDs) with two current sink drivers, or power four strings of WLEDs (about 24 WLEDs) with four current sink drivers. The duty ratio of PWM can be configured by software to adjust the backlight brightness. LCM0 uses the internal backlight driving circuit provided by SC600Y/SC600T by default. LCM1 can use the internal circuit or an external backlight driving circuit according to customers’ demands.
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Smart Module Series SC600Y&SC600T Hardware Design TP0_I2C_SCL 140 OD TP0 I2C clock 1.8V power domain. TP0_I2C_SDA 206 OD TP0 I2C data 1.8V power domain. TP1_INT 137 DI TP1 Interrupt 1.8V power domain. TP1_RST 136 DO TP1 reset Active low. TP1_I2C_SCL 205 OD TP1 I2C clock 1.8V power domain. TP1_I2C_SDA 204 OD TP1 I2C data 1.8V power domain. A reference design for touch panel interfaces is shown below.
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Smart Module Series SC600Y&SC600T Hardware Design 3.21. Camera Interfaces Based on standard MIPI CSI input interface, SC600Y/SC600T supports 3 cameras (4-lane + 4-lane + 4-lane) or 4 cameras (4-lane + 4-lane + 2-lane + 1-lane), with maximum pixels up to 21MP for SC600Y and 24MP for SC600T. The video and photo quality are determined by various factors such as camera sensor, camera lens quality, etc. Table 24: Pin Definition of Camera Interfaces Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design CSI0_LN3_P 96 AI MIPI lane 3 data signal of rear camera (+) CSI1_CLK_N 184 AO MIPI clock signal of depth camera (-) CSI1_CLK_P 183 AO MIPI clock signal of depth camera (+) CSI1_LN0_N 186 AI MIPI lane 0 data signal of depth camera (-) CSI1_LN0_P 185 AI MIPI lane 0 data signal of depth camera (+) CSI1_LN1_N 188 AI MIPI lane 1 data signal of depth camera (-) CSI1_LN1_P 187 AI MIPI lane 1 data signal of depth camera (+) CSI1_LN2_N 1
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Smart Module Series SC600Y&SC600T Hardware Design CSI2_LN3_N 86 AI MIPI lane 3 data signal of front camera (-) CSI2_LN3_P 85 AI MIPI lane 3 data signal of front camera (+) MCAM_MCLK 99 DO Master clock of rear camera 1.8V power domain. SCAM_MCLK 100 DO Master clock of front camera 1.8V power domain. MCAM_RST 74 DO Reset of rear camera 1.8V power domain. MCAM_PWDN 73 DO Power down of rear camera 1.8V power domain. SCAM_RST 72 DO Reset of front camera 1.8V power domain.
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Smart Module Series SC600Y&SC600T Hardware Design The following is a reference circuit design for dual camera applications. Figure 24: Reference Circuit Design for Dual Camera Applications NOTE CSI0 is used for rear camera, CSI1 is used for depth camera, and CSI2 is used for front camera.
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Smart Module Series SC600Y&SC600T Hardware Design The following is a reference circuit design for triple camera applications. Figure 25: Reference Circuit Design for Triple Camera Applications NOTE CSI1 data lines CSI1_LN2_P, CSI1_LN2_N, CSI1_LN3_P and CSI1_LN3_N can be multiplexed into MIPI signals for the fourth camera in four-camera application.
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Smart Module Series SC600Y&SC600T Hardware Design 3.21.1. Design Considerations     Special attention should be paid to the pin definition of LCM/camera connectors. Assure the SC600Y/SC600T and the connectors are correctly connected. MIPI are high speed signal lines, supporting maximum data rate up to 2.1Gbps. The differential impedance should be controlled as 100Ω. Additionally, it is recommended to route the trace on the inner layer of PCB, and do not cross it with other traces.
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Smart Module Series SC600Y&SC600T Hardware Design 105 DSI1_LN0_N 10.27 104 DSI1_LN0_P 10.16 107 DSI1_LN1_N 11.75 106 DSI1_LN1_P 11.58 109 DSI1_LN2_N 14.86 108 DSI1_LN2_P 14.5 111 DSI1_LN3_N 15.73 110 DSI1_LN3_P 15.88 89 CSI0_CLK_N 16.54 88 CSI0_CLK_P 16.57 91 CSI0_LN0_N 17.47 90 CSI0_LN0_P 17.4 93 CSI0_LN1_N 12.13 92 CSI0_LN1_P 12.08 95 CSI0_LN2_N 9.56 94 CSI0_LN2_P 9.7 97 CSI0_LN3_N 8.73 96 CSI0_LN3_P 8.86 184 CSI1_CLK_N 20.32 183 CSI1_CLK_P 20.
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Smart Module Series SC600Y&SC600T Hardware Design 192 CSI1_LN3_N 10.49 191 CSI1_LN3_P 10.06 78 CSI2_CLK_N 22.00 77 CSI2_CLK_P 22.17 80 CSI2_LN0_N 22.07 79 CSI2_LN0_P 22.00 82 CSI2_LN1_N 22.54 81 CSI2_LN1_P 22.05 84 CSI2_LN2_N 22.03 83 CSI2_LN2_P 21.92 86 CSI2_LN3_N 21.90 85 CSI2_LN3_P 22.49 -0.43 0.17 -0.07 -0.49 -0.11 0.59 3.21.2. Flashlight Interfaces SC600Y/SC600T supports 2 flash LED drivers. In Flash mode, the maximum output current is 0.
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Smart Module Series SC600Y&SC600T Hardware Design A reference circuit design is shown below. Figure 26: Reference Circuit Design for Flashlight Interfaces 3.22. Sensor Interfaces SC600Y/SC600T modules support communication with sensors via I2C interface, and it supports various sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor. Table 27: Pin Definition of Sensor Interfaces Pin Name Pin No. I/O Description Comment Dedicated for external sensors.
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Smart Module Series SC600Y&SC600T Hardware Design 3.23. Audio Interfaces SC600Y/SC600T provides three analog input channels and three analog output channels. The following table shows the pin definition. Table 28: Pin Definition of Audio Interfaces Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design 3.23.1.
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Smart Module Series SC600Y&SC600T Hardware Design 3.23.2. Reference Circuit Design for Earpiece Interface Figure 29: Reference Circuit Design for Earpiece Interface 3.23.3.
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Smart Module Series SC600Y&SC600T Hardware Design 3.23.4. Reference Circuit Design for Loudspeaker Interface F1 SPK_P EARP F2 EA SPK_N RN C1 C2 33pF 33pF D1 D2 Module Figure 31: Reference Circuit Design for Loudspeaker Interface 3.23.5. Audio Interfaces Design Considerations It is recommended to use the electret microphone with dual built-in capacitors (e.g. 10pF and 33pF) for filtering out RF interference, thus reducing TDD noise.
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Smart Module Series SC600Y&SC600T Hardware Design 3.24. Emergency Download Interface USB_BOOT is an emergency download interface. Pull up to LDO5_1P8 during power-up will force the module enter into emergency download mode. This is an emergency option when there are failures such as abnormal startup or operation. For convenient firmware upgrade and debugging in the future, please reserve the reference circuit design shown as below.
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Smart Module Series SC600Y&SC600T Hardware Design 4 Wi-Fi and BT SC600Y/SC600T provides a shared antenna interface ANT_WIFI/BT for Wi-Fi and Bluetooth (BT) functions. The interface impedance is 50Ω. External antennas such as PCB antenna, sucker antenna and ceramic antenna can be connected to the module via the interface, so as to achieve Wi-Fi and BT functions. 4.1. Wi-Fi Overview SC600Y/SC600T supports 2.4GHz and 5GHz dual-band WLAN wireless communication based on IEEE 802.
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Smart Module Series SC600Y&SC600T Hardware Design 802.11g 54Mbps 14dBm±2.5dB 802.11n HT20 MCS0 15dBm±2.5dB 802.11n HT20 MCS7 13dBm±2.5dB 802.11n HT40 MCS0 14dBm±2.5dB 802.11n HT40 MCS7 13dBm±2.5dB 802.11a 6Mbps 14dBm±2.5dB 802.11a 54Mbps 13dBm±2.5dB 802.11n HT20 MCS0 15dBm±2.5dB 802.11n HT20 MCS7 13dBm±2.5dB 802.11n HT40 MCS0 15dBm±2.5dB 802.11n HT40 MCS7 13dBm±2.5dB 802.11ac VHT20 MCS0 15dBm±2.5dB 802.11ac VHT20 MCS8 13dBm±2.5dB 802.11ac VHT40 MCS0 14dBm±2.
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Smart Module Series SC600Y&SC600T Hardware Design 5GHz 802.11n HT20 MCS7 -69dBm 802.11n HT40 MCS0 -85dBm 802.11n HT40 MCS7 -67dBm 802.11a 6Mbps -90dBm 802.11a 54Mbps -71dBm 802.11n HT20 MCS0 -86dBm 802.11n HT20 MCS7 -66dBm 802.11n HT40 MCS0 -84dBm 802.11n HT40 MCS7 -65dBm 802.11ac VHT20 MCS8 -65dBm 802.11ac VHT40 MCS9 -61dBm 802.11ac VHT80 MCS9 -56dBm Reference specifications are listed below:   IEEE 802.11n WLAN MAC and PHY, October 2009 + IEEE 802.
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Smart Module Series SC600Y&SC600T Hardware Design Table 31: BT Data Rate and Versions Refer ence specif icatio ns are listed below :    Version Data rate Maximum Application 1.2 1Mbit/s > 80Kbit/s 2.0+EDR 3Mbit/s > 80Kbit/s 3.0+HS 24Mbit/s Reference to 3.0+HS Throughput Comment B 4.0 24Mbit/s Reference to 4.0 LE lu e 4.2 60Mbit/s Reference to 4.2 LE t o oth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.
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Smart Module Series SC600Y&SC600T Hardware Design 5 GNSS SC600Y/SC600T integrates a Qualcomm IZat™ GNSS engine (Gen 8C) which supports multiple positioning and navigation systems including GPS, GLONASS and BeiDou. With an embedded LNA, the module provides greatly improved positioning accuracy. 5.1. GNSS Performance The following table lists the GNSS performance of SC600Y/SC600T module in conduction mode.
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Smart Module Series SC600Y&SC600T Hardware Design   capacitance such as 0.5pF can be selected. Otherwise, there will be effects on the impedance characteristic of RF circuit loop, or attenuation of bypass RF signal may be caused. Control the impedance of either feeder line or PCB trace as 50Ω, and keep the trace length as short as possible. Refer to Chapter 6.3 for GNSS antenna reference circuit designs.
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Smart Module Series SC600Y&SC600T Hardware Design 6 Antenna Interfaces SC600Y/SC600T provides five antenna interfaces for main antenna, Rx-diversity/MIMO antenna, GNSS antenna, Wi-Fi/BT antenna and FM antenna respectively. The antenna ports have an impedance of 50Ω. 6.1. Main/Rx-diversity Antenna Interfaces The pin definition of main/Rx-diversity antenna interfaces is shown below. Table 34: Pin Definition of Main/Rx-diversity Antenna Interfaces Pin Name Pin No.
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Smart Module Series SC600Y&SC600T Hardware Design Table 36: Wi-Fi/BT/FM Frequency 删除的内容: 39 Type Frequency A refere 2402~2482 nce 802.11a/b/g/n/ac 5180~5825 circuit desig BT4.2 LE 2402~2480 n for Wi-Fi/ FM 76~108 BT/F M antenna interface is shown as below. A π-type matching circuit is recommended to be performance. The capacitors are not mounted by default and resistors are 0Ω.
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Smart Module Series SC600Y&SC600T Hardware Design ency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz BeiDou 1561.098±2.046 MHz 6.3.1. Recommended Circuit for Passive Antenna GNSS antenna interface supports passive ceramic antennas and other types of passive antennas. A reference circuit design is given below.
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Smart Module Series SC600Y&SC600T Hardware Design Figure 36: Reference Circuit Design for GNSS Active Antenna 删除的内容: 41 6.4. Antenna Installation 6.4.1. Antenna Requirements The following table shows the requirements on main antenna, Rx-diversity, Wi-Fi/BT antenna and GNSS antenna.
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Smart Module Series SC600Y&SC600T Hardware Design U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. 删除的内容: 43 Figure 38: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. 删除的内容: 44 Figure 39: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
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Smart Module Series SC600Y&SC600T Hardware Design Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the space between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
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Smart Module Series SC600Y&SC600T Hardware Design Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:  Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω.
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Smart Module Series SC600Y&SC600T Hardware Design all the right-angle traces should be changed to curved ones.  There should be clearance under the signal pin of the antenna connector or solder joint.  The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times as wide as RF signal traces (2 W).
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Smart Module Series SC600Y&SC600T Hardware Design 7 Electrical, Reliability and Radio Characteristics 7.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. 删除的内容: 43 Table 40: Absolute Maximum Ratings Parameter Min Max Unit VBAT -0.5 6 V USB_VBUS -0.3 16 V 0 3 A 2.16 V Current on VBAT Voltage on Digital Pins -0.3 7.2.
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Smart Module Series SC600Y&SC600T Hardware Design IVBAT Peak supply current (during transmission slot) Maximum power control level at EGSM900 USB_VBUS VRTC Power supply voltage of backup battery 1.8 3.0 A 4.0 5.0 10 V 2.0 3.0 3.25 V 7.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. 删除的内容: 45 Table 42: Operation and Storage Temperatures Parameter Min Typ.
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Smart Module Series SC600Y&SC600T Hardware Design 7.4. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general. Consequently, it should be subject to ESD handling precautions that are typically applied to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. 删除的内容: Table 49: SC600Y-JP/SC600T-JP RF Output Power Frequency ...
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Smart Module Series SC600Y&SC600T Hardware Design 8 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimension tolerances are ±0.05mm unless otherwise specified. 8.1.
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Smart Module Series SC600Y&SC600T Hardware Design 删除的内容: 46 Figure 41: Module Bottom Dimensions (Top View) SC600Y&SC600T_Hardware_Design 111 / 134
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Smart Module Series SC600Y&SC600T Hardware Design 8.2. Recommended Footprint 删除的内容: 47 Figure 42: Recommended Footprint (Top View) NOTES 1. 2. For easy maintenance of the module, keep about 3mm between the module and other components on host PCB. All RESERVED pins should be kept open and MUST NOT be connected to ground.
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Smart Module Series SC600Y&SC600T Hardware Design 8.3. Top and Bottom View of the Module 删除的内容: 48 Figure 43: Top View of SC600Y/SC600T Module 删除的内容: 49 Figure 44: Bottom View of SC600Y/SC600T Module NOTE These are renderings of SC600Y/SC600T module. For authentic appearance, please refer to the module that you receive from Quectel.
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Smart Module Series SC600Y&SC600T Hardware Design 9 Storage, Manufacturing and Packaging 9.1. Storage SC600Y/SC600T is stored in a vacuum-sealed bag. They are rated at MSL 3, and their storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH.
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Smart Module Series SC600Y&SC600T Hardware Design 9.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.18mm~0.20mm.
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Smart Module Series SC600Y&SC600T Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 9.3. Packaging SC600Y/SC600T is packaged in tape and reel carriers. Each reel is 330mm in diameter and contains 200 modules. The following figures show the package details, measured in mm.
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Smart Module Series SC600Y&SC600T Hardware Design 删除的内容: 52 Figure 47: Reel Dimensions 删除的内容: 57 Table 45: Reel Packaging Model Name MOQ for MP SC600Y/ SC600T 200 Minimum Package: 200pcs Minimum Package×4=800pcs Size: 398mm × 383mm × 83mm Size: 420mm × 350mm × 405mm N.W: 1.92kg G.W: 3.67kg N.W: 8.18kg G.W: 15.
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Smart Module Series SC600Y&SC600T Hardware Design 10 Appendix A References 删除的内容: 58 Table 46: Related Documents SN Document Name Remark [1] Quectel_Smart_EVB-G2_User_Guide EVB User Guide for SC600Y/SC600T [2] Quectel_SC600Y&SC600T_GPIO_Configuration GPIO Configuration of SC600Y/SC600T [3] Quectel_RF_Layout_Application_Note RF Layout Application Note [4] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide [5] Quectel_ SC600Y&SC600T_Reference_Design Reference Design for
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Smart Module Series SC600Y&SC600T Hardware Design DRX Discontinuous Reception EFR Enhanced Full Rate ESR Equivalent Series Resistance ESD Electrostatic Discharge ERM Eccentric Rotating Mass FR Full Rate GLONASS Globalnaya Navigazionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GPS Global Positioning System GPU Graphics Processing Unit HR 删除的内容: EGSM ... [13] 删除的内容: GMSK ... [14] Half Rate 删除的内容: GSM ... [15] IO Input / Output 删除的内容: HSDPA ...
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Smart Module Series SC600Y&SC600T Hardware Design RF Radio Frequency RH Relative Humidity RHCP Right Hand Circularly Polarized RTC Real Time Clock Rx Receive SMS Short Message Service TE Terminal Equipment TX Transmitting Direction UART Universal Asynchronous Receiver & Transmitter UL Uplink (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VI Voltage Input VIHmin Minimum Input High Level Voltage Val
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Smart Module Series SC600Y&SC600T Hardware Design 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the user’s body and must not transmit simultaneously with any other antenna or transmitter. 3.A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR201911SC600WF. 4. This module must not transmit simultaneously with any other antenna or transmitter 5.
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Smart Module Series SC600Y&SC600T Hardware Design §15.19 Labeling requirements. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. 带格式的: 英语(美国) §15.21 Information to user.
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页 5: [1] 删除的内容 dell 2019/12/5 10:12:00 About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ..............................................................................................................................................
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3.23. Audio Interfaces ........................................................................................................................ 81 3.23.1. Reference Circuit Design for Microphone Interfaces ..................................................... 82 3.23.2. Reference Circuit Design for Earpiece Interface ........................................................... 83 3.23.3. Reference Circuit Design for Headphone Interface ....................................................... 83 3.23.4.
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9.3. 10 11 12 13 Packaging................................................................................................................................ 125 Appendix A References................................................................................................................... 127 Appendix B GPRS Coding Schemes ............................................................................................. 131 Appendix C GPRS Multi-slot Classes ..............................................
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TABLE 38: PIN DEFINITION OF WI-FI/BT/FM ANTENNA INTERFACE ......................................................... 98 TABLE 39: WI-FI/BT/FM FREQUENCY .......................................................................................................... 98 TABLE 40: PIN DEFINITION OF GNSS ANTENNA ........................................................................................ 99 TABLE 41: GNSS FREQUENCY .............................................................................................
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页 13: [5] 删除的内容 dell LTE-FDD B1/B3/B5/B8/B11/B18/B19/B21/B26/B28A/B28B LTE-TDD B41 WCDMA B1/B6/B8/B19 GSM / 页 13: [6] 删除的内容 dell LTE-FDD / LTE-TDD / WCDMA / GSM / 页 14: [7] 删除的内容 Memory 页 14: [8] 删除的内容 dell 2019/12/6 9:32:00 2019/12/6 9:33:00 2019/12/6 10:16:00 16GB eMMC + 2GB LPDDR3 (default) 32GB eMMC + 3GB LPDDR3 (optional) 64GB eMMC + 4GB LPDDR3 (optional) dell Transmitting Power Class 4 (33dBm±2dB) for GSM850 Class 4 (33dBm±2dB) for EGSM900 Class 1 (30dBm±2dB) for DCS1800 Cl
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UMTS Features Support 3GPP R9 DC-HSDPA/DC-HSUPA/HSPA+/HSDPA/HSUPA/WCDMA Support QPSK, 16-QAM and 64-QAM modulation DC-HSDPA: Max 42Mbps (DL) DC-HSUPA: Max 11.2Mbps (UL) WCDMA: Max 384Kbps (DL)/Max 384Kbps (UL) GSM Features R99 CSD: 9.6kbps, 14.4kbps GPRS Support GPRS multi-slot class 33 (33 by default) Coding scheme: CS-1, CS-2, CS-3 and CS-4 Max 107Kbps (DL), 85.
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LTE-TDD B26 758~788 703~733 MHz LTE-FDD B28A 758~788 703~733 MHz LTE-FDD B28B 773~803 718~748 MHz LTE-TDD B41 1) 2496~2690 2496~2690 MHz Table 36: SC600Y-EM/SC600T-EM Operating Frequencies 3GPP Band Receive Transmit Unit GSM850 869~894 824~849 MHz EGSM900 925~960 880~915 MHz DCS1800 1805~1880 1710~1785 MHz PCS1900 1930~1990 1850~1910 MHz WCDMA B1 2110~2170 1920~1980 MHz WCDMA B2 1930~1990 1850~1910 MHz WCDMA B4 2110~2155 1710~1755 MHz WCDMA B5 869~894 824~84
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LTE-FDD B28B 773~803 718~748 MHz LTE-TDD B38 2570~2620 2570~2620 MHz LTE-TDD B39 1880~1920 1880~1920 MHz LTE-TDD B40 2300~2400 2300~2400 MHz LTE-TDD B41 1) 2496~2690 2496~2690 MHz Table 37: SC600Y-NA/SC600T-NA Operating Frequencies 3GPP Band Receive Transmit Unit WCDMA B2 1930~1990 1850~1910 MHz WCDMA B4 2110~2155 1710~1755 MHz WCDMA B5 869~894 824~849 MHz LTE-FDD B2 1930~1990 1850~1910 MHz LTE-FDD B4 2110~2155 1710~1755 MHz LTE-FDD B5 869~894 824~849 MHz LTE-
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NOTE 1) The bandwidth of LTE-TDD B41 for SC600Y-EM/SC600T-EM, SC600Y-JP/SC600T-JP, SC600Y-NA/SC600T-NA is 200MHz (2496MHz~2690MHz), and the corresponding channel ranges from 39650 to 41589. Main and Rx-diversity Antenna Interfaces Reference Design A reference circuit design for main and Rx-diversity antenna interfaces is shown as below.
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structures.
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Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pins, and should be fully connected to ground.
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Cable Insertion Loss: <2dB (LTE-FDD B7, LTE-TDD B38/B40/B41) 页 108: [11] 删除的内容 dell 2019/12/6 9:29:00 Table 46: SC600Y-JP/SC600T-JP Current Consumption Parameter Description Conditions OFF state Power down 80 uA Sleep (USB disconnected) @DRX=6 4.57 mA Sleep (USB disconnected) @DRX=8 3.1 mA Sleep (USB disconnected) @DRX=9 3.0 mA Sleep (USB disconnected) @DRX=6 4.13 mA Sleep (USB disconnected) @DRX=8 3.15 mA Sleep (USB disconnected) @DRX=6 3.
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B19 (HSUPA) @max power 600 mA LTE-FDD B1 @max power 570 mA LTE-FDD B3 @max power 610 mA LTE-FDD B5 @max power 530 mA LTE-FDD B8 @max power 540 mA LTE-TDD B11 @max power 550 mA LTE-TDD B18 @max power 595 mA LTE-TDD B19 @max power 540 mA LTE-TDD B21 @max power 560 mA LTE-TDD B26 @max power 570 mA LTE-TDD B28A @max power 680 mA LTE-TDD B28B @max power 625 mA LTE-TDD B41 @max power 530 mA LTE data transfer Table 47: SC600Y-EM/SC600T-EM Current Consumption Parameter Descr
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LTE-TDD supply current Sleep (USB disconnected) @DRX=8 2.96 mA Sleep (USB disconnected) @DRX=6 4.27 mA Sleep (USB disconnected) @DRX=8 3.
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EGSM900 (2UL/3DL) @PCL 5 380 mA EGSM900 (3UL/2DL) @PCL 5 490 mA EGSM900 (4UL/1DL) @PCL 5 520 mA DCS1800 (1UL/4DL) @PCL 0 190 mA DCS1800 (2UL/3DL) @PCL 0 280 mA DCS1800 (3UL/2DL) @PCL 0 350 mA DCS1800 (4UL/1DL) @PCL 0 420 mA PCS1900 (1UL/4DL) @PCL 0 190 mA PCS1900 (2UL/3DL) @PCL 0 290 mA PCS1900 (3UL/2DL) @PCL 0 370 mA PCS1900 (4UL/1DL) @PCL 0 420 mA GSM850 (1UL/4DL) @PCL 8 170 mA GSM850 (2UL/3DL) @PCL 8 250 mA GSM850 (3UL/2DL) @PCL 8 320 mA GSM850 (4UL/1DL) @PCL 8
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WCDMA data transfer LTE data transfer PCS1900 (3UL/2DL) @PCL 2 400 mA PCS1900 (4UL/1DL) @PCL 2 410 mA B1 (HSDPA) @max power 550 mA B2 (HSDPA) @max power 510 mA B4 (HSDPA) @max power 530 mA B5 (HSDPA) @max power 550 mA B8 (HSDPA) @max power 510 mA B1 (HSUPA) @max power 580 mA B2 (HSUPA) @max power 530 mA B4 (HSUPA) @max power 550 mA B5 (HSUPA) @max power 520 mA B8 (HSUPA) @max power 520 mA LTE-FDD B1 @max power 550 mA LTE-FDD B2 @max power 530 mA LTE-FDD B3 @max po
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LTE-TDD B41 @max power mA 580 Table 48: SC600Y-NA/SC600T-NA Current Consumption Parameter Description Conditions OFF state Power down 80 uA Sleep (USB disconnected) @DRX=6 3.72 mA Sleep (USB disconnected) @DRX=8 3.08 mA Sleep (USB disconnected) @DRX=9 2.60 mA Sleep (USB disconnected) @DRX=6 3.84 mA Sleep (USB disconnected) @DRX=8 3.0 mA Sleep (USB disconnected) @DRX=6 4.19 mA Sleep (USB disconnected) @DRX=8 2.
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LTE-FDD B7 @max power 710 mA LTE-FDD B12 @max power 520 mA LTE-FDD B13 @max power 540 mA LTE-TDD B14 @max power 560 mA LTE-TDD B17 @max power 470 mA LTE-TDD B25 @max power 530 mA LTE-TDD B26 @max power 590 mA LTE-TDD B66 @max power 620 mA LTE-TDD B71 @max power 580 mA LTE-TDD B41 @max power 450 mA RF Output Power The following table shows the RF output power of SC600Y/SC600T module.
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LTE-FDD B11 23dBm±2dB <-39dBm LTE-FDD B18 23dBm±2dB <-39dBm LTE-FDD B19 23dBm±2dB <-39dBm LTE-FDD B21 23dBm±2dB <-39dBm LTE-FDD B26 23dBm±2dB <-39dBm LTE-FDD B28A 23dBm±2dB <-39dBm LTE-FDD B28B 23dBm±2dB <-39dBm LTE-TDD B41 23dBm±2dB <-39dBm Table 50: SC600Y-EM/SC600T-EM RF Output Power Frequency Max Min GSM850 33dBm±2dB 5dBm±5dB EGSM900 33dBm±2dB 5dBm±5dB DCS1800 30dBm±2dB 0dBm±5dB PCS1900 30dBm±2dB 0dBm±5dB WCDMA B1 24dBm+1/-3dB <-49dBm WCDMA B2 24dBm+1/-3dB <-4
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LTE-FDD B8 23dBm±2dB <-39dBm LTE-FDD B20 23dBm±2dB <-39dBm LTE-FDD B28A 23dBm±2dB <-39dBm LTE-FDD B28B 23dBm±2dB <-39dBm LTE-TDD B38 23dBm±2dB <-39dBm LTE-TDD B39 23dBm±2dB <-39dBm LTE-TDD B40 23dBm±2dB <-39dBm LTE-TDD B41 23dBm±2dB <-39dBm Table 51: SC600Y-NA/SC600T-NA RF Output Power Frequency Max Min WCDMA B2 24dBm+1/-3dB <-49dBm WCDMA B4 24dBm+1/-3dB <-49dBm WCDMA B5 24dBm+1/-3dB <-49dBm LTE-FDD B2 23dBm±2dB <-39dBm LTE-FDD B4 23dBm±2dB <-39dBm LTE-FDD B5 23dBm
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NOTE In GPRS 4 slots TX mode, the maximum output power is reduced by 3dB. This design conforms to the GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of SC600Y/SC600T module. Table 52: SC600Y-JP/SC600T-JP RF Receiving Sensitivity Frequency Receive Sensitivity (Typ.) 3GPP (SIMO) Primary Diversity SIMO WCDMA B1 -108.5 -109.5 -110.5 -106.7dBm WCDMA B6 -109.5 -108 -111 -106.
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LTE-TDD B41 (10M) -95 -96 -98 -94.3dBm Table 53: SC600Y-EM/SC600T-EM RF Receiving Sensitivity Receive Sensitivity (Typ.) Frequency 3GPP (SIMO) Primary Diversity SIMO GSM850 -109 / / -102.4dBm EGSM900 -108 / / -102.4dBm DCS1800 -107 / / -102.4dBm PCS1900 -107 / / -102.4dBm WCDMA B1 -109 -109 -110 -106.7dBm WCDMA B2 -109 -109 -110 -106.7dBm WCDMA B4 -109 -108.5 -110 -104.7dBm WCDMA B5 -109.5 -108 -110.5 -104.7dBm WCDMA B8 -109 -109 -110.5 -104.
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Table 54: SC600Y-NA/SC600T-NA RF Receiving Sensitivity Frequency Receive Sensitivity (Typ.) 3GPP (SIMO) Primary Diversity SIMO WCDMA B2 -109 -109 -111 -106.7dBm WCDMA B4 -109 -109 -110.5 -104.7dBm WCDMA B5 -109.5 -109.5 -111 -104.7dBm LTE-FDD B2 (10M) -97 -97 -99.5 -94.3dBm LTE-FDD B4 (10M) -97 -96.5 -98.5 -96.3dBm LTE-FDD B5 (10M) -98 -97.5 -100 -94.3dBm LTE-FDD B7 (10M) -96 -96 -98 -94.3dBm LTE-FDD B12 (10M) -96 -97.5 -98.5 -93.3dBm LTE-FDD B13 (10M) -95.
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页 119: [14] 删除的内容 GMSK dell Gaussian Minimum Shift Keying 页 119: [15] 删除的内容 GSM dell dell HSDPA High Speed Down Link Packet Access HSPA High Speed Packet Access 页 119: [17] 删除的内容 dell dell 2019/12/6 10:22:00 2019/12/6 10:23:00 Time Division Distortion 页 120: [19] 删除的内容 UMTS 2019/12/6 10:22:00 Long-Term Evolution Time-Division Duplex 页 120: [18] 删除的内容 TDD 2019/12/6 10:22:00 Global System for Mobile Communications 页 119: [16] 删除的内容 LTE-TDD 2019/12/6 10:22:00 dell 2019/12/6 10:23:00 U
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Appendix B GPRS Coding Schemes Table 60: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 分节符(下一页)
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Appendix D EDGE Modulation and Coding Schemes Table 62: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.8kbps 29.6kbps 59.