BG77 Hardware Design LPWA Module Series Rev. BG77_Hardware_Design_V1.1 Date: 2019-10-08 Status: Preliminary www.quectel.
LPWA Module Series BG77 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
LPWA Module Series BG77 Hardware Design About the Document History Revision Date Author Description 1.0 2019-06-17 Jake JIANG/ Newgate HUA Initial 1. 2. 3. 4. 5. 1.1 2019-10-08 BG77_Hardware_Design Lyndon LIU/ Watt ZHU 6. 7. 8. 9. 10. 11. Delete GNSS optional information. Updated the power supply in Table 3. Updated Pin Assignment in Figure 2. Updated Pin Description in Table 3. Added PON_TRIG pin to wake-up the module from PSM in Chapter 3.4.2. Updated the power supply in Chapter 3.5.
LPWA Module Series BG77 Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ............................................................................................................................................
LPWA Module Series BG77 Hardware Design 3.15. 3.16. 3.17. 3.18. 3.19. 3.20. Behaviors of RI* ..................................................................................................................... 45 USB_BOOT Interface ............................................................................................................. 45 ADC Interfaces ....................................................................................................................... 46 SPI Interface* ...........
LPWA Module Series BG77 Hardware Design Table Index TABLE 1: FREQUENCY BANDS AND GNSS TYPES OF BG77 MODULE..................................................... 11 TABLE 2: KEY FEATURES OF BG77 MODULE .............................................................................................. 12 TABLE 3: DEFINITION OF I/O PARAMETERS ................................................................................................ 17 TABLE 4: PIN DESCRIPTION ..................................................
LPWA Module Series BG77 Hardware Design TABLE 42: RECOMMENDED THERMAL PROFILE PARAMETERS .............................................................. 71 TABLE 43: REEL PACKAGING ........................................................................................................................ 73 TABLE 44: RELATED DOCUMENTS ............................................................................................................... 74 TABLE 45: TERMS AND ABBREVIATIONS ..............................
LPWA Module Series BG77 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 14 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 16 FIGURE 3: SLEEP MODE APPLICATION VIA UART ......................................................................................
LPWA Module Series BG77 Hardware Design FIGURE 39: REEL DIMENSIONS .....................................................................................................................
LPWA Module Series BG77 Hardware Design 1 Introduction This document defines BG77 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document can help customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG77. To facilitate its application in different fields, reference design is also provided for customers’ reference.
LPWA Module Series BG77 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG77. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
1.2 FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
❒ NB LTE Band12/85:≤12.416dBi ❒ NB LTE Band13:≤11.734dBi ❒ BNLTE Band14:≤12.272 dBi ❒NB LTE Band71:≤11.447 dBi ❒NB LTE Band85:≤12.770 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible; then an additional permanent label referring to the enclosed module:“Contains Transmitter Module FCC ID: XMR201912BG77” or “Contains FCC ID: XMR201912BG77” must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID.
LPWA Module Series BG77 Hardware Design 2 Product Concept 2.1. General Description BG77 is an embedded IoT (LTE Cat M1, LTE Cat NB2) wireless communication module. It provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also provides GNSS and voice 1) functionality to meet customers’ specific application demands.
LPWA Module Series BG77 Hardware Design 2.2. Key Features The following table describes the detailed features of BG77 module. Table 2: Key Features of BG77 Module Features Details Power Supply Transmitting Power Class 5 (21dBm+1/-3dB) for LTE-FDD bands LTE Features Support 3GPP Rel. 14 Support LTE Cat M1 and LTE Cat NB2 Support 1.4MHz RF bandwidth for LTE Cat M1 Support 200KHz RF bandwidth for LTE Cat NB2on Cat M1: Max. 588Kbps (DL)/1119Kbps (UL) Cat NB2: Max. 127Kbps (DL)/158.
LPWA Module Series BG77 Hardware Design Used for software debugging and log output Support 115200bps baud rate GNSS UART: Used for GNSS data and NMEA sentences output 115200bps baud rate by default AT Commands 3GPP TS 27.007 and 3GPP TS 27.
LPWA Module Series BG77 Hardware Design ANT_MAIN ANT_GNSS COUPLER SAW+LNA GNSS Transceiver/PA/switch VBAT IQ PWRKEY PMIC Control Control RESET_N Baseband PON_TRIG ADC1 ADC0 19.2M XO VDD_EXT USB (U)SIM PCM UARTs I2C GPIOs SPI STATUS NETLIGHT Figure 1: Functional Diagram NOTES 1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY.
LPWA Module Series BG77 Hardware Design 3 Application Interfaces BG77 is equipped with 94 LGA pads that can be connected to customers’ cellular application platforms. The following sub-chapters will provide detailed description of interfaces listed below: Power supply (U)SIM interface USB interface UART interfaces PCM and I2C interfaces* Status indication USB_BOOT interface ADC interfaces GPIO interfaces* GRFC interfaces* NOTE “*” means under development.
LPWA Module Series BG77 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG77.
LPWA Module Series BG77 Hardware Design 3. 4. 5. 6. 7. 8. ADC input voltage must not exceed 1.8V The input voltage range of USB_VBUS is 1.3V~1.8V. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. W_DISABEL#, AP_READY, USIM_DET, PCM, I2C, GRFC and GPIO functions are under development. SPI_MOSI(pin40), NETLIGHT(pin79) and GPRC1(pin83) are BOOT_CONFIG pins, They should not be pulled up before startup. 3.2.
LPWA Module Series BG77 Hardware Design VDD_EXT 21 GND 22~25, 27, 28, 30, 31, 43, 47, 52~56, 58, 66, 73~75, 84~86, 88, 89 PO 1.8V output power supply for external circuit Vnorm=1.8V IOmax=50mA Power supply for external GPIO’s pull-up circuits. If unused, keep this pin open. Ground Turn on/off Pin No. I/O Description DC Characteristics Comment 46 DI Turn on/off the module Vnorm=1.5V VILmax=0.45V PWRKEY should never be pulled down to GND permanently. Pin Name Pin No.
LPWA Module Series BG77 Hardware Design No. VIHmax=1.8V VIHmin=1.3V USB_VBUS 12 AI USB detection USB_DP 11 IO USB differential data bus (+) USB_DM 10 IO USB differential data bus (-) USB_VDDA_3P3 42 PI Power for USB PHY circuit Vnorm=3.3V EXT_PWR_EN 64 DO External LDO enable of USB VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Pin No. I/O Description DC Characteristics Comment VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open.
LPWA Module Series BG77 Hardware Design VIHmax=2.0V RXD 6 DI Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. TXD 7 DO Transmit data VOLmax=0.45V VOHmin=1.35V CTS 39 DO Clear to send VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. DI Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open.
LPWA Module Series BG77 Hardware Design PCM Interface* Pin Name PCM_CLK PCM_SYNC PCM_DIN PCM_DOUT Pin No. I/O Description DC Characteristics Comment DO PCM clock output VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. DO PCM frame synchronization output VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. DI PCM data input VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open.
LPWA Module Series BG77 Hardware Design SPI_MOSI 40 DO SPI master-out slave-in VOLmax=0.45V VOHmin=1.35V BOOT_CONFIG. Do not pull it up before startup . 1.8V power domain. If unused, keep this pin open. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. SPI_MISO 8 DI SPI master-in slave-out SPI_CS_N 63 DO SPI chip select VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. 1.8V power domain.
LPWA Module Series BG77 Hardware Design to digital converter interface ADC1 18 AI General purpose analog to digital converter interface Pin No. I/O Description Voltage range: 0.1V to 1.8V If unused, keep this pin open. DC Characteristics Comment Airplane mode control VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Pulled up by default. When it is in low voltage level, the module can enter into airplane mode. If unused, keep this pin open.
LPWA Module Series BG77 Hardware Design interface 94 DO General RF control interface Pin Name Pin No. I/O Description RESERVED 29, 48~51, 59, 67~71, 80~82, 91~93 GRFC2 before startup 1.8V power domain. If unused, keep this pin open. VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. DC Characteristics Comment RESERVED Pins Reserved Keep these pins open. NOTES 1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset.
LPWA Module Series BG77 Hardware Design Table 5: Overview of Operating Modes Mode Normal Operation Details Connected Network has been connected. In this mode, the power consumption may vary with the network setting and data transfer rate. Idle Software is active. The module remains registered on network, and it is ready to send and receive data.
LPWA Module Series BG77 Hardware Design Hardware: W_DISABLE# is pulled up by default. Driving it to low level will let the module enter into airplane mode. Software: AT+CFUN= provides choice of the functionality level, through setting into 0, 1 or 4. AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled. AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. RF function is disabled. NOTES 1.
LPWA Module Series BG77 Hardware Design 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value.
LPWA Module Series BG77 Hardware Design Figure 3: Sleep Mode Application via UART When BG77 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for details about RI behavior. Driving the host DTR to low level will wake up the module. AP_READY will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG="apready" command in document [2] for details. NOTE AP_READY function is still under development. 3.5.
LPWA Module Series BG77 Hardware Design 3.5.2. Decrease Voltage Drop The power supply range of BG77 is from 2.6V to 4.8V. Please make sure that the input voltage will never drop below 2.6V. To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR.
LPWA Module Series BG77 Hardware Design “*” means under development. 3.6. Power on and off Scenarios 3.6.1. Turn on Module Using the PWRKEY Pin The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 46 Description DC Characteristics Comment Turn on/off the module Vnorm=1.5V VILmax=0.45V The output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset.
LPWA Module Series BG77 Hardware Design Figure 6: Turn on the Module Using Keystroke The power on timing is illustrated in the following figure. NOTE VBA T PWRKEY 500ms~1000ms VIL≤0.45V RESET_N Typ. 2.1s STATUS (DO) Typ. 2.55s USB Inactive Active Typ. 2.5s UART Inactive Active Figure 7: Timing of Turning on Module NOTES 1. Make sure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30ms. 2. PWRKEY output voltage is 1.
LPWA Module Series BG77 Hardware Design 3.6.2. Turn off Module Either of the following methods can be used to turn off the module: Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using AT+QPOWD command. 3.6.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage for a duration between 650ms and 1500ms, the module will execute power-down procedure after the PWRKEY is released.
LPWA Module Series BG77 Hardware Design The module can be reset by driving RESET_N low for a duration between 2s and 3.8s. Table 8: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 45 Reset the module VILmax=0.45V Multiplexed from PWRKEY. The reset timing is illustrated in the following figure. VBA T ≤3.8s ≥2s RESET_N VIL≤0.
LPWA Module Series BG77 Hardware Design S2 RESET_N TVS Close to S2 Figure 11: Reference Circuit of RESET_N by Using Button NOTES Please assure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG Interface BG77 provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects a rising edge, the module will be woken up from PSM. Table 9: Pin Definition of PON_TRIG Interface Pin Name PON_TRIG Pin No.
LPWA Module Series BG77 Hardware Design VDD_1V8 10K 10K PON_TRIG_MCU 100K 100K PON_TRIG Figure 12: Reference Circuit of PON_TRIG Circuit NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG77 supports 1.8V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 10: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET 44 DI (U)SIM card insertion detection 1.8V power domain. The pin function development.
LPWA Module Series BG77 Hardware Design BG77 supports (U)SIM card hot-plug via USIM_DET. The function supports low level or high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET command for details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.
LPWA Module Series BG77 Hardware Design criteria below in (U)SIM circuit design: Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.
LPWA Module Series BG77 Hardware Design USB_VDDA_3P3 42 PI Power supply for USB PHY circuit Vnorm=3.3V EXT_PWR_EN 64 DO External LDO enable of USB 1.8V power domain GND 43 Ground For more details about USB 2.0 specification, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in customers’ design. The following figures illustrate reference designs of USB PHY and USB interface.
LPWA Module Series BG77 Hardware Design A common mode choke L1 is recommended to be added in series between the module and customer’s MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be added in series between the module and the test points so as to facilitate debugging, and the resistors are not mounted by default.
LPWA Module Series BG77 Hardware Design Table 12: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment DTR 62 DI Data terminal ready. Sleep mode control. 1.8V power domain RXD 6 DI Receive data 1.8V power domain TXD 7 DO Transmit data 1.8V power domain CTS 39 DO Clear to send 1.8V power domain RTS 38 DI Request to send 1.8V power domain DCD 90 DO Data carrier detection 1.8V power domain RI 76 DO Ring indication signal 1.
LPWA Module Series BG77 Hardware Design Table 15: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V The module provides 1.8V UART interfaces. A level translator should be used if customers’ application is equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design of the Main UART interface: VDD_EXT VCCA 120K VCCB 10K 0.
LPWA Module Series BG77 Hardware Design Figure 18: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12. PCM and I2C Interfaces* BG77 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No.
LPWA Module Series BG77 Hardware Design The following figure shows a reference design of PCM and I2C interfaces with an external codec IC. PCM_CLK BCLK PCM_SYNC WCLK PCM_DIN ADC PCM_DOUT DAC I2C_SCL SCL I2C_SDA SDA INP INN BIAS MICBIAS Module 4.7K 4.7K LOUTP LOUTN Codec 1.8V Figure 19: Reference Circuit of PCM Application with Audio Codec NOTE “*” means under development. 3.13. Network Status Indication BG77 provides one network status indication pin: NETLIGHT.
LPWA Module Series BG77 Hardware Design Flicker slowly (200ms High/1800ms Low) Network searching Flicker slowly (1800ms High/200ms Low) Idle Flicker quickly (125ms High/125ms Low) Data transfer is ongoing Always high Voice calling NETLIGHT A reference circuit is shown in the following figure. VBAT Module 2.2K NETLIGHT 4.7K 47K Figure 20: Reference Circuit of the Network Status Indicator NOTES NETLIGHT is a BOOT_CONFIG pin. It should not be pulled up before startup. 3.14.
LPWA Module Series BG77 Hardware Design Figure 21: Reference Circuit of STATUS 3.15. Behaviors of RI* AT+QCFG="risignaltype","physical" command can be used to configure RI behavior. No matter on which port URC is presented, URC will trigger the behavior of RI pin. The default behaviors of RI are shown as below. Table 20: Default Behaviors of RI State Response Idle RI keeps in high level. URC RI outputs 120ms low pulse when new URC returns.
LPWA Module Series BG77 Hardware Design BG77 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the module to boot from USB port for firmware upgrade. Table 21: Pin Definition of USB_BOOT Interface Pin Name USB_BOOT Pin No. 87 I/O Description Comment DI Force the module to enter into emergency download mode 1.8V power domain. Active high. If unused, keep it open. The following figure shows a reference circuit of USB_BOOT interface.
LPWA Module Series BG77 Hardware Design Table 22: Pin Definition of ADC Interfaces Pin Name Pin No. Description ADC0 17 General purpose analog to digital converter interface ADC1 18 General purpose analog to digital converter interface The following table describes the characteristics of ADC interfaces. Table 23: Characteristics of ADC Interfaces Parameter Min. Voltage Range 0.1 Typ. Max. Unit 1.8 V Resolution (LSB) 64.979 uV Analog Bandwidth 500 kHz Sample Clock 4.
LPWA Module Series BG77 Hardware Design Table 24: Pin Definition of SPI Interface Pin Name Pin No. I/O Description Comment SPI_MOSI 40 DO SPI master-out slave-in BOOT_CONFIG. Do not pull it up before startup. 1.8V power domain SPI_MISO 8 DI SPI master-in slave-out 1.8V power domain SPI_CS_N 63 DO SPI chip select 1.8V power domain SPI_CLK 9 DO SPI clock 1.8V power domain NOTES 1. SPI_MOSI cannot be pulled up before the module powers up. 2. The module provides 1.8V SPI interface.
LPWA Module Series BG77 Hardware Design VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V NOTE “*” means under development. 3.20. GRFC Interfaces* The module provides two general RF control interfaces. Those can be used for control external antenna tuner. This function is under development. Table 27: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 83 General RF control interface BOOT_CONFIG. Do not pull it up before startup. 1.8V power domain.
LPWA Module Series BG77 Hardware Design 4 GNSS Receiver 4.1. General Description BG77 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). BG77 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, BG77 GNSS engine is switched off. It has to be switched on via AT command.
LPWA Module Series BG77 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @open sky TBD m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
LPWA Module Series BG77 Hardware Design 5 Antenna Interfaces BG77 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 30: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 26 IO Main antenna interface 50Ω characteristic impedance 5.1.2.
LPWA Module Series BG77 Hardware Design LTE-FDD B13 777~787 746~756 MHz LTE-FDD B14 1) 788~798 758~768 MHz LTE-FDD B18 815~830 860~875 MHz LTE-FDD B19 830~845 875~890 MHz LTE-FDD B20 832~862 791~821 MHz LTE-FDD B25 1850~1915 1930~1995 MHz LTE-FDD B26* 814~849 859~894 MHz LTE-FDD B27 1) 807~824 852~869 MHz LTE-FDD B28 703~748 758~803 MHz LTE-FDD B66 1710~1780 2110~2180 MHz LTE-FDD B71 2) 663~698 617~652 MHz LTE-FDD B85 698~716 728~746 MHz NOTES 1.
LPWA Module Series BG77 Hardware Design Figure 23: Reference Circuit of RF Antenna Interface 5.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S).
LPWA Module Series BG77 Hardware Design Figure 25: Coplanar Waveguide Line Design on a 2-layer PCB Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) BG77_Hardware_Design 55 / 76
LPWA Module Series BG77 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
LPWA Module Series BG77 Hardware Design Figure 28: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna.
LPWA Module Series BG77 Hardware Design Cable Insertion Loss: < 1dB (LTE B5/B8/B12/B13/B14 2)/B18/B19/B20/B26*/B27 2)/B28/B71 3)/ B85) Cable Insertion Loss: < 1.5dB (LTE B1/B2/B3/B4/B25/B66) NOTES 1. 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3. 3) LTE-FDD B71 is supported by Cat NB2 only. 4.
LPWA Module Series BG77 Hardware Design Figure 30: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 31: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
LPWA Module Series BG77 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 35: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT -0.5 6.0 V USB_VBUS 1.3 1.8 V Voltage at Digital Pins -0.3 2.09 V Description Conditions Min. Typ. Max.
LPWA Module Series BG77 Hardware Design 6.3. Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 37: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range 1) -35 +25 +75 ºC Extended Temperature Range 2) -40 +85 ºC Storage Temperature Range -40 +90 ºC NOTES 1. 2. 1) Within operation temperature range, the module is 3GPP compliant.
LPWA Module Series BG77 Hardware Design DRX=1.28s TBD TBD mA DRX=1.28s TBD TBD mA e-I-DRX=81.92s TBD TBD mA e-I-DRX=81.92s TBD TBD mA DRX=1.28s TBD TBD mA DRX=1.28s TBD TBD mA e-I-DRX=20.48s TBD TBD mA e-I-DRX=20.
LPWA Module Series BG77 Hardware Design LTE Cat NB2 data transfer (GNSS OFF) LTE-FDD B85 @TBDdBm TBD TBD mA LTE-FDD B1 @TBDdBm TBD TBD mA LTE-FDD B2 @TBDdBm TBD TBD mA LTE-FDD B3 @TBDdBm TBD TBD mA LTE-FDD B4 @TBDdBm TBD TBD mA LTE-FDD B5 @TBDdBm TBD TBD mA LTE-FDD B8 @TBDdBm TBD TBD mA LTE-FDD B12 @TBDdBm TBD TBD mA LTE-FDD B13 @TBDdBm TBD TBD mA LTE-FDD B18 @TBDdBm TBD TBD mA LTE-FDD B19 @TBDdBm TBD TBD mA LTE-FDD B20 @TBDdBm TBD TBD mA LTE-FDD B25 @TBDdBm
LPWA Module Series BG77 Hardware Design Table 39: BG77 RF Output Power Frequency Max. LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B14 1)/B18/B19/B20/B25/ B26/B27 2) /B28/B66/B71/B85 21dBm+1/-3dB Min. <-39dBm NOTES 1. 2. 3. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. LTE-FDD B71 is supported by Cat NB2 only. “*” means under development. 2) 6.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG77.
LPWA Module Series BG77 Hardware Design LTE-FDD B20 TBD/-99.8 TBD/-107.5 LTE-FDD B25 TBD/-100.3 TBD/-107.5 LTE-FDD B26* TBD/-100.3 TBD/-107.5 LTE-FDD B27 2) TBD/-100.8 NOT Supported LTE-FDD B28 TBD/-100.8 TBD/-107.5 LTE-FDD B66 TBD/-101.8 TBD/-107.5 NOT Supported TBD/-107.5 TBD/-99.3 TBD/-107.5 LTE-FDD B71 3) LTE-FDD B85 NOTES 1. 1) LTE Cat NB2 receiving sensitivity without repetitions. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3.
LPWA Module Series BG77 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are ±0.05mm. 7.1. Mechanical Dimensions of the Module 12.90±0.15 1.7±0.2 14.90±0.
LPWA Module Series BG77 Hardware Design 12.90±0.15 11.90 1.00 6.45 1.00 R0.35 Pin 1 7.45 13.90 1.95 1.30 7.45 0.85 6.45 5.30 4.15 14.90±0.15 0.85 0.65 0.65 0.65 1.15 R0.35 1.30 6.
LPWA Module Series BG77 Hardware Design 7.2. Recommended Footprint 12.90±0.15 11.90 1.00 6.45 1.00 R0.35 Pin 1 7.45 0.65 13.90 1.30 1.95 7.45 6.45 5.30 4.15 14.90±0.15 0.85 0.85 0.65 0.65 1.15 1.30 6.45 R0.35 Figure 34: Recommended Footprint (Top View) NOTES 1. 2. 3. For easy maintenance of the module, please keep about 3mm between the module and other components on the host PCB. Keep all reserved pins open. For stencil design requirements of the module, please refer to document [5].
LPWA Module Series BG77 Hardware Design 7.3. Design Effect Drawings of the Module Figure 35: Top View of the Module Figure 36: Bottom View of the Module NOTE These are renderings of BG77 module. For authentic appearance, please refer to the module that you receive from Quectel.
LPWA Module Series BG77 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG77 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10%RH. 3.
LPWA Module Series BG77 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [5].
LPWA Module Series BG77 Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging BG77 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The following figures show the packaging details, measured in mm.
LPWA Module Series BG77 Hardware Design Figure 39: Reel Dimensions Table 43: Reel Packaging Model Name MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs BG77 TBD TBD TBD BG77_Hardware_Design 73 / 76
LPWA Module Series BG77 Hardware Design 9 Appendix A References Table 44: Related Documents SN Document Name Remark [1] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide [2] Quectel_BG77_AT_Commands_Manual BG77 AT Commands Manual [3] Quectel_BG77_GNSS_AT_Commands_Manual BG77 GNSS AT Commands Manual [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 45: Terms and Abbreviations Abbreviat
LPWA Module Series BG77 Hardware Design ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol D
LPWA Module Series BG77 Hardware Design TX Transmitting Direction UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Abso
