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Smart LTE Module Series
SC650T Hardware Design
SC650T_Hardware_Design 48 / 131
the OTG device is attached: when USB_ID is kept open (high level by default), SC650T is in USB slave
mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply power for
peripherals with maximum output of 5V/1A.
The following is a reference design for USB interface:
USB_DP
USB_DM
USB_VUSB
1
2
3
4
5
USB_DP
USB_DM
VUSB
USB_ID
GND
GND
GND
GND
GND
6
7 8
9
100nF
Module
C1
D1
D2 D3
ESD ESD ESD
USB_ID
Figure 11: USB 2.0 Interface Reference Design
USB_DP
100nF
Module
C14
Switch
C2
C3
C4
C5
A0+
A0-
A1+
A0-
B0+
B0-
B1+
B1-
C0+
C0-
C1+
C1-
SEL
PD
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
CC_OUT
R1
VDD
4.7uF
C1
VDD_3V
TX2+
TX2-
VBUS_ VBUS
CC
1
D+
D-
RX2-
RX2+
CC2
CC1
CC2
TX1+
TX1-
RX1+
RX1-
USB 3.0
C6
C7
C8
C9
C10
C11
C12
C13
USB_DM
USB_ VBUS
Figure 12: USB Type-C Interface Reference Design
In order to ensure USB performance, please follow the following principles while designing USB interface.
 It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
 Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines.
Typically, the capacitance value should be less than 2pF for USB 2.0 and less than 0.5pF for USB
3.0.
 Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is