Product Info

Smart LTE Module Series
SC650T Hardware Design
SC650T_Hardware_Design 63 / 131
The following are the reference designs for LCM interfaces.
DSI0_CLK_N
116
AO
LCD0 MIPI clock signal
(negative)
DSI0_CLK_P
115
AO
LCD0 MIPI clock signal
(positive)
DSI0_LN0_N
118
AO
LCD0 MIPI lane 0 data signal
(negative)
DSI0_LN0_P
117
AO
LCD0 MIPI lane 0 data signal
(positive)
DSI0_LN1_N
120
AO
LCD0 MIPI lane 1 data signal
(negative)
DSI0_LN1_P
119
AO
LCD0 MIPI lane 1 data signal
(positive)
DSI0_LN2_N
122
AO
LCD0 MIPI lane 2 data signal
(negative)
DSI0_LN2_P
121
AO
LCD0 MIPI lane 2 data signal
(positive)
DSI0_LN3_N
124
AO
LCD0 MIPI lane 3 data signal
(negative)
DSI0_LN3_P
123
AO
LCD0 MIPI lane 3 data signal
(positive)
DSI1_CLK_N
103
AO
LCD1 MIPI clock signal
(negative)
DSI1_CLK_P
102
AO
LCD1 MIPI clock signal
(positive)
DSI1_LN0_N
105
AO
LCD1 MIPI lane 0 data signal
(negative)
DSI1_LN0_P
104
AO
LCD1 MIPI lane 0 data signal
(positive)
DSI1_LN1_N
107
AO
LCD1 MIPI lane 1 data signal
(negative)
DSI1_LN1_P
106
AO
LCD1 MIPI lane 1 data signal
(positive)
DSI1_LN2_N
109
AO
LCD1 MIPI lane 2 data signal
(negative)
DSI1_LN2_P
108
AO
LCD1 MIPI lane 2 data signal
(positive)
DSI1_LN3_N
111
AO
LCD1 MIPI lane 3 data signal
(negative)
DSI1_LN3_P
110
AO
LCD1 MIPI lane 3 data signal
(positive)