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ManualsBrandsQuectel ManualsElectronicsLTE-A Cat 18 LGA Module

EG18 Hardware Design

LTE-A Module Series

Rev. EG18_Hardware_Design_V1.1

Date: 2019-12-21

Status: Released

www.quectel.com

Summary of content (111 pages)

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EG18 Hardware Design LTE-A Module Series Rev. EG18_Hardware_Design_V1.1 Date: 2019-12-21 Status: Released www.quectel.
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LTE-A Module Series EG18 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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LTE-A Module Series EG18 Hardware Design About the Document History Revision Date Author Description 1.0 2019-07-25 Oscar LIU/ Xavier XIA Initial 1. 2. 1.1 2019-12-21 EG18_Hardware_Design Archibald JIANG/ Xavier XIA 3.
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LTE-A Module Series EG18 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index .....................................................................................................................................
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LTE-A Module Series EG18 Hardware Design 3.11. SPI Interface*........................................................................................................................... 53 3.12. PCM and I2C Interfaces .......................................................................................................... 55 3.13. ADC Interfaces ........................................................................................................................ 57 3.14. Network Status Indication .......
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LTE-A Module Series EG18 Hardware Design 7 Mechanical Dimensions .................................................................................................................... 93 7.1. Mechanical Dimensions of the Module.................................................................................... 93 7.2. Recommended Footprint ......................................................................................................... 95 7.3. Design Effect Drawings of the Module ...................
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LTE-A Module Series EG18 Hardware Design Table Index TABLE 1: FREQUENCY BANDS, CA COMBINATIONS AND GNSS TYPES OF EG18 MODULE................. 12 TABLE 2: KEY FEATURES OF EG18............................................................................................................... 14 TABLE 3: I/O PARAMETERS DEFINITION ...................................................................................................... 20 TABLE 4: PIN DESCRIPTION ........................................................
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LTE-A Module Series EG18 Hardware Design TABLE 42: EG18-NA CURRENT CONSUMPTION .......................................................................................... 85 TABLE 43: RF OUTPUT POWER ..................................................................................................................... 87 TABLE 44: EG18-EA CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 87 TABLE 45: EG18-NA CONDUCTED RF RECEIVING SENSITIVITY ..................
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LTE-A Module Series EG18 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 19 FIGURE 3: DRX RUN TIME AND CURRENT CONSUMPTION IN SLEEP MODE ......................................... 32 FIGURE 4: SLEEP MODE APPLICATION VIA UART INTERFACES ..............
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LTE-A Module Series EG18 Hardware Design FIGURE 40: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) ................................................................................................................................................................... 77 FIGURE 41: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) .......................................................................................................................................
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LTE-A Module Series EG18 Hardware Design 1 Introduction This document defines EG18 module and describes its air interface and hardware interfaces which are connected to customers’ applications. This document helps customers quickly understand interface specifications, electrical and mechanical details, as well as other related technical information of EG18 module. Associated with relevant application notes and user guides, the module will be used to design and set up mobile applications easily.
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LTE-A Module Series EG18 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating EG18 module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals supplied with the product.
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LTE-A Module Series EG18 Hardware Design 2 Product Concept 2.1. General Description EG18 is a series LTE-FDD/LTE-TDD/WCDMA wireless communication module with diversity reception. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. EG18 supports embedded operating systems such as Windows, Linux and Android. It also provides GNSS 1) and voice functionality 2) to meet specific application demands. The module comprises two variants: EG18-EA and EG18-NA.
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LTE-A Module Series EG18 Hardware Design 3×CA (DL) B1+B3+B3/B5/B7/B8/B20/B28/B38/B41; B1+B40+B40; B1+B41+B41; B1+B7+B20; B3+B3+B7/B20/B28; B3+B7+B7/B8/B20/B28; B3+B40+B40; B3+B41+B41; B7+B7+B20/B28; B40+B40+B40; B41+B41+B41 B2+B4+B5*/B13*/B71*; B2+B5+B66; B2+B12+B30; B2+B13+B66; B2+B7+B12/B66; B4+B30+B5/B12/B29; B4+B7+B12; B30+B66+B5/B12/B29; B2+B2+B5/B12/B13/B29/B66; B5+B5+B2/B30/B66; B7+B7+B2/B4/B5; B66+B66+B2/B5/B13/B66; B41+B41+B25/B26/B41; 4×CA (DL) B1+B3+B3+B5/B7/B8/B28/B41; B1+B3+B7+B5/B7/B8/B20
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LTE-A Module Series EG18 Hardware Design 2.2. Key Features The following table describes the detailed features of EG18. Table 2: Key Features of EG18 Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.
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LTE-A Module Series EG18 Hardware Design Support master and slave modes, but must be the master in long frame synchronization USB Interface UART Interfaces Comply with USB 3.0 and 2.0 specifications, with maximum transmission rates up to 5Gbps on USB 3.0 and 480Mbps on USB 2.0 Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output, and voice over USB* Support USB serial drivers for: Windows 7/8/8.1/10; Linux 2.6/3.x/4.1~4.15; Android 4.x/5.
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LTE-A Module Series EG18 Hardware Design NOTES 1. 2. 3. “*” means under development. 1) Within operating temperature range, the module is 3GPP compliant. 2) Within extended temperature range, proper mounting, heating sinks and active cooling may be required to make certain functions of the module such as voice, SMS, data transmission to be realized. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances.
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LTE-A Module Series EG18 Hardware Design 2.4. Evaluation Board To help with the development of applications with EG18, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, earphone, antenna, and other peripherals to control or test the module. For more details, please refer to document [2].
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LTE-A Module Series EG18 Hardware Design 3 Application Interfaces EG18 is designed with 299 LGA pins that can be connected to cellular application platform.
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LTE-A Module Series EG18 Hardware Design 3.1.
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LTE-A Module Series EG18 Hardware Design NOTES 1. 2. Keep all RESERVED pins and unused pins unconnected. The GND pins 215~299 should be connected to ground in the design. 3.2. Pin Description Table 3: I/O Parameters Definition Type Description AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output The following table exhibits the pin definition and description of EG18.
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LTE-A Module Series EG18 Hardware Design If an SD card is used, connect VDD_P2 to SD_VDD. If an eMMC* is used or SDIO interface is unused, connect VDD_P2 to VDD_EXT. SD card power supply VDD_P2 135 PI VDD_EXT 168 PO Provide 1.8V for external circuit. Vnorm=1.8V IOmax=50mA VDD_RF 162 PO Provide 2.85V for external RF circuit. Vnorm=2.
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LTE-A Module Series EG18 Hardware Design Status Indication Pin Name NET_MODE NET_STATUS STATUS Pin No. I/O Description DC Characteristics Comment DO Indicate the module’s network registration mode. VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open. DO Indicate the module’s network activity status. VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open. 171 DO Indicate the module’s operation status. VOHmin=1.35V VOLmax=0.45V 1.8V power domain.
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LTE-A Module Series EG18 Hardware Design (U)SIM1 card VILmax=0.36V VIHmin=1.26V VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM: VILmax=0.57V VIHmin=2.0V VOLmax=0.4V VOHmin=2.3V For 1.8V (U)SIM: Vmax=1.9V Vmin=1.7V USIM2_VDD USIM2_DATA USIM2_DET USIM2_RST USIM2_CLK 74 77 78 79 80 EG18_Hardware_Design PO IO DI DO DO Power supply for (U)SIM2 card Data signal of (U)SIM2 card (U)SIM2 card insertion detection Reset signal of (U)SIM2 card Clock signal of (U)SIM2 card For 3.0V (U)SIM: Vmax=3.
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LTE-A Module Series EG18 Hardware Design For 3.0V (U)SIM: VOLmax=0.4V VOHmin=2.3V USB Interface Pin Name Pin No. I/O Description DC Characteristics Vmax=5.25V Vmin=3.3V Vnorm=5.0V USB_VBUS 32 DI USB connection detection USB_DM 33 IO USB 2.0 differential data bus (-) USB_DP 34 IO USB 2.0 differential data bus (+) USB_SS_ TX_M 37 AO USB 3.0 super speed transmission (-) USB_SS_ TX_P 38 AO USB 3.0 super speed transmission (+) USB_SS_ RX_P 40 AI USB 3.
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LTE-A Module Series EG18 Hardware Design 1) SD_DATA2 47 IO SDIO data signal (bit 2) SD_DATA3 48 IO SDIO data signal (bit 3) SD_CMD 51 DO SDIO command signal SD_CLK 53 DO SDIO clock signal SD_ DET 52 VILmin=-0.3V VILmax=0.58V VIHmin=1.3V VIHmax=2.0V For 3.0V SD card: VOLmax=0.35V VOHmin=2.15V VILmin=-0.3V VILmax=0.7V VIHmin=1.8V VIHmax=3.15V open. If unused, keep it open. If unused, keep it open. If unused, keep it open. If unused, keep it open.
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LTE-A Module Series EG18 Hardware Design will wake up the module. If unused, keep it open. Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. DBG_RXD 136 DI Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V DBG_TXD 137 DO Transmit data VOLmax=0.45V VOHmin=1.35V BT UART Interface (Can be multiplexed into SPI interface*) Pin Name BT_EN BT_TXD BT_CTS Pin No.
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LTE-A Module Series EG18 Hardware Design VIHmin=1.2V VIHmax=2.0V open. BT UART interface pin by default. Can be multiplexed into SPI_CS. PCM & I2C Interfaces Pin Name Pin No. I/O Description I2C_SDA 42 OD I2C_SCL 43 OD I2C serial interface used for external codec PCM_SYNC PCM_IN 65 IO 66 DI DC Characteristics 1.8V power domain. An external pull-up resistor is required. If unused, keep it open. PCM data frame synchronization signal VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.
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LTE-A Module Series EG18 Hardware Design ANT_ MIMO1 101 AI Support all band 4x4 MIMO antenna interface them open. ANT_MIMO2 113 AI Support all band 4x4 MIMO antenna interface ANT_GNSS 119 AI GNSS antenna interface I/O Description DC Characteristics Comment DO WLAN power supply enable control VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DO LTE/WLAN coexistence signal VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open.
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LTE-A Module Series EG18 Hardware Design PCIe Interface* Pin Name I/O Description PCIE_REFCLK_P 179 AI/ AO Input/Output PCIe reference clock (+) PCIE_REFCLK_ M 180 AI/ AO Input/Output PCIe reference clock (-) PCIE_TX_M 182 AO PCIe transmission (-) PCIE_TX_P 183 AO PCIe transmission (+) PCIE_RX_M 185 AI PCIe receiving (-) PCIE_RX_P 186 AI PCIe receiving (+) PCIE_CLK_ REQ_N PCIE_RST_N PCIE_WAKE_N Pin No. 188 189 IO IO DC Characteristics Comment Comply with PCIe 2.
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LTE-A Module Series EG18 Hardware Design Antenna Tuner Control Interfaces* (RFFE Interface/GPIO Interface) Pin Name Pin Name I/O RFFE_CLK 71 DO RFFE_DATA 73 IO GPIO_3 159 IO Description DC Characteristics Comment VOLmax=0.45V VOHmin=1.35V RFFE serial interface used for external tuner control VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V If unused, keep them open. VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.
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LTE-A Module Series EG18 Hardware Design RESERVED Pins Pin Name Pin No. RESERVED 4, 6~9, 11, 12, 14, 15, 18~23, 72, 91, 95, 134, 176, 192~195, 197~201, 209~213 I/O Description DC Characteristics Reserved Comment Keep these pins unconnected. 3.3. Operating Modes The table below summarizes different operating modes of EG18. Table 5: Overview of Operating Modes Mode Details Normal Operation Modes Idle Software is active.
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LTE-A Module Series EG18 Hardware Design 3.4. Power Saving 3.4.1. Sleep Mode Current Consumption DRX of EG18 is able to reduce the current consumption to a minimum value during the sleep mode, and DRX cycle index values are broadcasted by the wireless network. The figure below shows the relationship between the DRX run time and the current consumption in sleep mode. The longer the DRX cycle is, the lower the current consumption will be.
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LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Host Module RXD TXD TXD RXD RI EINT DTR GPIO GND GND Figure 4: Sleep Mode Application via UART Interfaces   Driving the host DTR to low level will wake up the module. When EG18 has a URC to report, RI signal will wake up the host. Please refer to Chapter 3.16 for details about RI behaviors. 3.4.1.2.
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LTE-A Module Series EG18 Hardware Design   Sending data to EG18 through USB will wake up the module. When EG18 has a URC to report, the module will send remote wake-up signals via USB bus to wake up the host. 3.4.1.3. USB Application with USB Suspend/Resume and RI Function If the host supports USB suspend/resume, but does not support remote wake-up function, RI signal is needed to wake up the host. There are three preconditions to make the module enter into sleep mode.
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LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Module Host GPIO USB_VBUS Power Switch USB Interface VDD USB Interface RI EINT GND GND Figure 7: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match of the connection shown in dotted line between the module and the host. 3.4.2.
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LTE-A Module Series EG18 Hardware Design Low Level AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 RF Disabled Airplane mode NOTES 1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol" command, and this command is under development. 2. The execution of AT+CFUN command will not affect GNSS function. 3.5. Power Supply 3.5.1. Power Supply Pins EG18 provides six VBAT pins dedicated to the connection with an external power supply.
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LTE-A Module Series EG18 Hardware Design 3.5.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V. Please make sure the input voltage will never drop below 3.3V. The following figure shows the maximum voltage drop when burst transmission occurs during radio transmission in 3G and 4G networks. Max Tx Power Max Tx Power VCC Ripple Drop Min. 3.
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LTE-A Module Series EG18 Hardware Design 3.5.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply of EG18 should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, an LDO is suggested to be used to supply power for the module.
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LTE-A Module Series EG18 Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Turn on the Module Through PWRKEY The following table shows the pin definition of PWRKEY. Table 8: PWRKEY Pin Description Pin Name PWRKEY Pin No. 2 Description DC Characteristics Comment Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V 1.8V power domain. Pulled-up internally. Active low.
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LTE-A Module Series EG18 Hardware Design Another way to control the PWRKEY is using a button. Electrostatic strike may generate from fingers when the button is pressed. Therefore, it is necessary to place a TVS component nearby the button for ESD protection. A reference circuit is shown by the following figure: S1 PWRKEY TVS Close to S1 Figure 12: Turn on the Module Using a Button The timing of turn-on scenario is illustrated by the following figure. NOTE VBAT ≥500ms PWRKEY VIH≥1.3V VIL≤0.
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LTE-A Module Series EG18 Hardware Design 3.6.2. Turn off the Module The following two methods can be used to turn off the module: through PWRKEY or AT+QPOWD command. 3.6.2.1. Turn off the Module Through PWRKEY Driving PWRKEY to a low level voltage for at least 800ms, then the module will execute power-down procedure after the PWRKEY is released. The timing of turn-off scenario is illustrated by the following figure. VBAT ≥800ms ≥30s PWRKEY STATUS ≥10s VDD_EXT ≥1.5s VDD_RF ≥1.
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LTE-A Module Series EG18 Hardware Design NOTES 1. 2. To avoid damages to the internal flash, please do not switch off the power supply directly when the module is working. Only after the module is shut down by PWRKEY or AT command can the power supply be cut off. When turning off the module with AT command, please keep PWRKEY at high level after execution of the power-off command. Otherwise, the module will be turned on again after a successful turning-off. 3.7.
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LTE-A Module Series EG18 Hardware Design S2 RESET_N TVS Close to S2 Figure 16: Reference Circuit of RESET_N with a Button The timing of reset scenario is illustrated by the following figure. VBAT ≤600ms VIH≥1.3V RESET_N VIL≤0.5V ≥212.5ms ≥2.5ms VDD_EXT ≥204ms ≥17s VDD_RF ≥205ms ≥16s USIM_VDD ≥250ms Module Status Running Resetting Restart Figure 17: Timing of Resetting the Module NOTES 1. 2.
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LTE-A Module Series EG18 Hardware Design 3.8. (U)SIM Interfaces EG18 provides two (U)SIM interfaces. The circuitry of (U)SIM interfaces meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported. Dual SIM Single Standby function is supported and (U)SIM card switching is enabled by AT+QUIMSLOT command. For more details about this command, please refer to document [3]. Table 10: Pin Definition of the (U)SIM Interfaces Pin Name Pin No.
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LTE-A Module Series EG18 Hardware Design The following figure shows a reference design for a (U)SIM interface with an 8-pin (U)SIM card connector. VDD_EXT USIM_VDD 51K 15K 100nF (U)SIM Card Connector USIM_VDD Module USIM_RST 22R USIM_CLK USIM_DET 22R USIM_DATA 22R CLK GND VPP IO CD1 CD2 VCC RST GND NM NM NM GND Figure 18: Reference Circuit of a (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET pins unconnected.
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LTE-A Module Series EG18 Hardware Design The (U)SIM scenario is illustrated by the following figure. ≥5.8ms USIM_VDD ≥1.1ms USIM_DATA ATR ≥1.7ms USIM_CLK ≥20.8ms USIM_RST Figure 20: Timing of (U)SIM When AT+QSIMDET=1,0 is set, the scenario of hot-plug is illustrated by the following figure. USIM_DET ≥103ms ≥5.8ms USIM_VDD ≥1.1ms ATR USIM_DATA ≥1.7ms USIM_CLK ≥20.
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LTE-A Module Series EG18 Hardware Design      Keep (U)SIM card signals away from RF and VBAT traces. Keep the ground traces between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground.
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LTE-A Module Series EG18 Hardware Design For more details about the USB 2.0 and USB 3.0 specifications, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in design. The following figure shows a reference circuit of USB 2.0 and USB 3.0 interface.
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LTE-A Module Series EG18 Hardware Design The USB enumeration scenario is illustrated by the following figure. STATUS USB_VBUS ≥525ms USB Inactive ≥200ms Enumeration procedure Active Figure 23: Timing of USB Enumeration The following principles of USB interface should be complied with, so as to meet USB 2.0 and USB 3.0 specifications.       It is important to route the USB 2.0 & 3.0 signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90Ω.
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LTE-A Module Series EG18 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: main UART interface, debug UART interface, and BT UART interface. Features of these interfaces are shown as below:    Main UART interface supports 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps (default), 230400bps, 460800bps, and 921600bps baud rates. It is used for data transmission and AT command communication. And it supports RTS and CTS hardware flow control.
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LTE-A Module Series EG18 Hardware Design 3.10.2. Debug UART Interface The following table shows the pin definition of debug UART interface. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 136 DI Receive data 1.8V power domain DBG_TXD 137 DO Transmit data 1.8V power domain 3.10.3. BT UART Interface The following table shows the pin definition of BT UART interface. Table 14: Pin Definition of the BT UART Interface Pin Name Pin No.
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LTE-A Module Series EG18 Hardware Design VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design. VDD_EXT VCCA 0.1μF 10K VCCB 0.
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LTE-A Module Series EG18 Hardware Design Another example with transistor translation circuit is shown as below. The circuit designs for the parts shown with dotted lines refer to the design of TXD and RXD, and please pay attention to the direction of connection. 4.7K VDD_EXT VDD_EXT 1nF MCU/ARM 10K Module TXD RXD RXD TXD 1nF 10K VCC_MCU VDD_EXT 4.
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LTE-A Module Series EG18 Hardware Design BT_RXD 165 DI Can be multiplexed into SPI_MISO. BT_RTS 166 DI Can be multiplexed into SPI_CS. The following figure shows the timing of SPI Interface. T t(ch) t(cl) SPI_CS_N 1 SPI_CLK 3 2 4 MSB SPI_MOSI t(mov) t(mis) t(mih) SPI_MISO Figure 26: Timing of SPI Interface The related parameters of SPI timing are listed in the following table. Table 17: Parameters of SPI Interface Timing Parameter Description Min. Typ. Max.
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LTE-A Module Series EG18 Hardware Design 3.12. PCM and I2C Interfaces EG18 supports audio communication via Pulse Code Modulation (PCM) digital interface and I2C interfaces. The PCM interface supports the following modes:   Primary mode (short frame synchronization, works as both master and slave) Auxiliary mode (long frame synchronization, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge.
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LTE-A Module Series EG18 Hardware Design 125μs PCM_CLK 1 2 31 32 PCM_SYNC MSB LSB MSB LSB PCM_OUT PCM_IN Figure 28: Auxiliary Mode Timing The following table shows the pin definition of PCM interface and I2C interface, both of which can be applied on audio codec design. Table 18: Pin Definition of PCM interface and I2C Interface Pin Name Pin No. I/O Description Comment PCM_IN 66 DI PCM data input 1.8V power domain. If unused, keep it open. PCM_OUT 68 DO PCM data output 1.
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LTE-A Module Series EG18 Hardware Design Clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to document [3] for details about AT+QDAI command. The following figure shows a reference design of PCM interface with an external codec IC. PCM_CLK BCLK PCM_SYNC LRCK PCM_OUT DAC PCM_IN ADC I2C_SCL SCL I2C_SDA SDA INP INN BIAS MICBIAS 4.7K Module 4.
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LTE-A Module Series EG18 Hardware Design In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground. Table 19: Pin Definition of the ADC Interfaces Pin Name Pin No. Description ADC0 173 General purpose analog to digital converter interface. If unused, keep it open. ADC1 175 General purpose analog to digital converter interface If unused, keep it open. The following table describes characteristics of ADC interfaces.
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LTE-A Module Series EG18 Hardware Design NET_STATUS 170 DO Indicate the module’s network activity status. 1.8V power domain If unused, keep it open.
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LTE-A Module Series EG18 Hardware Design 3.15. Operation Status Indication The STATUS pin is set as the module status indicator. It outputs high level voltage when the module is turned on. The following table describes pin definition of STATUS pin. Table 23: Pin Definition of STATUS Pin Name STATUS Pin No. 171 I/O Description Comment DO Indicate the module’s operation status 1.8V power domain If unused, keep it open. A reference circuit is shown as below. VBAT Module 2.2K STATUS 4.
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LTE-A Module Series EG18 Hardware Design In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below. Table 24: RI Behaviors State Response Idle RI keeps at high level URC RI outputs 120ms low pulse when a new URC returns The RI behavior can be changed by executing AT+QCFG="urc/ri/ring" command. Please refer to document [3] for more details. 3.17.
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LTE-A Module Series EG18 Hardware Design PCIE_CLK_REQ_N PCIE_RST_N PCIE_WAKE_N 188 189 190 IO IO IO PCIe clock request In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. PCIe reset In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. PCIe wake In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open.
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LTE-A Module Series EG18 Hardware Design 3.17.1. Root Complex Mode In this mode, the module is configured to act as a PCIe RC device. The following figure shows a reference circuit of PCIe RC mode.
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LTE-A Module Series EG18 Hardware Design 3.17.2. Endpoint Mode In this mode, the module is configured to act as a PCIe EP device. The following figure shows a reference circuit of PCIe EP mode.
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LTE-A Module Series EG18 Hardware Design    matching should be less than 2mm (15ps). For PCIe signal traces, the maximum length of each differential data pair (TX/RX) is recommended to be less than 250mm, and each differential data pair matching should be less than 0.7mm (5ps). Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces.
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LTE-A Module Series EG18 Hardware Design The following figure shows an SDIO interface reference design.
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LTE-A Module Series EG18 Hardware Design 3.19. Antenna Tuner Control Interfaces* The module provides two methods to control external antenna tuner: through RFFE signals or GPIO signals. Customers can choose either one according to their tuner design. The following table lists the pin definitions of these RFFE and GPIO signals. Table 27: Pin Definition of RFFE Interface Used to Control Antenna Tuner Pin Name Pin No.
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LTE-A Module Series EG18 Hardware Design GPIO_5 172 IO VDD_RF 162 PO If unused, keep it open. Provide 2.85V for external RF circuit. If unused, keep it open. NOTE “*” means under development. 3.20. USB_BOOT Interface EG18 provides a USB_BOOT pin. Developers can pull up USB_BOOT to VDD_EXT before powering on the module, to make the module enter into emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB interface.
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LTE-A Module Series EG18 Hardware Design 3.21. GPIOs In addition to the three GPIOs dedicated for external tuner control, the module provides 2 GPIOs for customers’ design. Table 30: Pin Definition of GPIOs Pin Name Pin No. I/O GPIO_1 138 IO GPIO_2 139 IO Description Comment If unused, keep it open. General purpose input/output port EG18_Hardware_Design If unused, keep it open.
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LTE-A Module Series EG18 Hardware Design 4 GNSS Receiver 4.1. General Description EG18 includes a fully integrated global navigation satellite system solution that supports Gen9HT-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EG18 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, EG18 GNSS engine is switched off. It has to be switched on via AT command.
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LTE-A Module Series EG18 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous 3 s XTRA enabled 2 s Autonomous @open sky 1.5 m 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers’ design.     Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antennas.
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LTE-A Module Series EG18 Hardware Design 5 Antenna Interfaces EG18 provides a main antenna interface, an Rx-diversity antenna interface, two MIMO antenna interfaces, and a GNSS antenna interface. The impedance of antenna ports is 50Ω. 5.1. Main/Rx-diversity/MIMO Antenna Interfaces 5.1.1. Pin Definition The pin definition of main antenna interface, Rx-diversity antenna interface and MIMO antenna interfaces is shown as below.
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LTE-A Module Series EG18 Hardware Design LTE B1 1920~1979.9 2110~2169.9 MHz LTE B3 1710~1784.9 1805~1879.9 MHz LTE B5 824~848.9 869~893.9 MHz LTE B7 2500~2569.9 2620~2689.9 MHz LTE B8 880~914.9 925~959.9 MHz LTE B20 832~861.9 791~820.9 MHz LTE B28 703~747.9 758~802.9 MHz LTE B38 2570~2619.9 2570~2619.9 MHz LTE B40 2300~2399.9 2300~2399.9 MHz LTE B41 2496~2689.9 2496~2689.
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LTE-A Module Series EG18 Hardware Design LTE B30 2305~2315 2350~2360 MHz LTE B41 2496~2689.9 2496~2689.9 MHz LTE B66 1710~1780 2110~2200 MHz LTE B71 617~652 663~698 MHz 5.1.3. Reference Design of RF Antenna Interfaces A reference design of ANT_MAIN, ANT_DIV, ANT_MIMO1 and ANT_MIMO2 interfaces is shown as below. It should reserve a π-type matching circuit for better RF performance.
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LTE-A Module Series EG18 Hardware Design 5.2. GNSS Antenna Interface 5.2.1. Pin Definition The following tables show pin definition and frequency specification of GNSS antenna interface. Table 35: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 119 AI GNSS antenna interface 50Ω impedance 5.2.2. GNSS Frequency Table 36: GNSS Frequency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz Galileo 1575.42±2.046 MHz BeiDou 1561.
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LTE-A Module Series EG18 Hardware Design 5.2.3. Reference Design of GNSS Antenna Interface A reference design of GNSS antenna is shown as below. VDD 0.1μF 10R Module GNSS Antenna 47nH 100pF 0R ANT_GNSS NM NM Figure 37: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed.
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LTE-A Module Series EG18 Hardware Design 5.3. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
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LTE-A Module Series EG18 Hardware Design Figure 41: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
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LTE-A Module Series EG18 Hardware Design Active antenna gain: >0dBi Active antenna embedded LNA gain: <17dB VSWR: ≤ 2 Efficiency: >30% Max Input Power: 50W Input Impedance: 50Ω Cable Insertion Loss: <1dB (WCDMA B5/B8/, LTE B5/B8/B12/B13/B14/B20/B26/B28/B29/B71) Cable Insertion Loss: <1.
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LTE-A Module Series EG18 Hardware Design U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT. Figure 43: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mating plugs. Figure 44: Space Factor of Mating Plugs (Unit: mm) For more details, please visit http://www.hirose.com.
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LTE-A Module Series EG18 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 38: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 1.2 A Peak Current of VBAT_RF 0 1.5 A Voltage at Digital Pins -0.3 2.3 V Voltage at ADC0 0 1.
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LTE-A Module Series EG18 Hardware Design 6.2. Power Supply Ratings Table 39: The Module’s Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF The actual input voltages must stay between the minimum and maximum values. 3.3 3.8 4.3 V USB_VBUS USB connection detection 3.3 5.0 5.25 V 6.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table.
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LTE-A Module Series EG18 Hardware Design 6.4. Current Consumption 6.4.1. EG18-EA Current Consumption Table 41: EG18-EA Current Consumption Parameter Description Conditions Typ. Unit IVBAT OFF state Power down 20 μA AT+CFUN=0 (USB disconnected) 0.98 mA WCDMA PF=64 (USB disconnected) 2.51 mA WCDMA PF=128 (USB disconnected) 1.94 mA WCDMA PF=256 (USB disconnected) 1.62 mA WCDMA PF=512 (USB disconnected) 1.49 mA LTE-FDD PF=32 (USB disconnected) 4.
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LTE-A Module Series EG18 Hardware Design IVBAT IVBAT IVBAT WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) WCDMA voice call LTE-TDD PF=64 (USB active) 24.97 mA WCDMA B1 HSDPA CH10700 @23.4dBm 460 mA WCDMA B1 HSUPA CH10700 @23.5dBm 460 mA WCDMA B3 HSDPA CH1338 @23.3dBm 502 mA WCDMA B3 HSUPA CH1338 @23.4dBm 508 mA WCDMA B5 HSDPA CH4407 @23.4dBm 558 mA WCDMA B5 HSUPA CH4407 @23.3dBm 539 mA WCDMA B8 HSDPA CH3012 @23.3dBm 569 mA WCDMA B8 HSUPA CH3012 @23.
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LTE-A Module Series EG18 Hardware Design 6.4.2. EG18-NA Current Consumption Table 42: EG18-NA Current Consumption Parameter Description Conditions Typ. Unit IVBAT OFF state Power down 15 μA AT+CFUN=0 (USB disconnected) 1.08 mA WCDMA PF=64 (USB disconnected) 2.53 mA WCDMA PF=128 (USB disconnected) 2.05 mA WCDMA PF=256 (USB disconnected) 1.81 mA WCDMA PF=512 (USB disconnected) 1.7 mA LTE-FDD PF=32 (USB disconnected) 4.55 mA LTE-FDD PF=64 (USB disconnected) 3.
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LTE-A Module Series EG18 Hardware Design IVBAT IVBAT IVBAT WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) WCDMA voice call WCDMA B2 HSDPA CH9800 @22.89dBm 678.24 mA WCDMA B2 HSUPA CH9800 @22.94dBm 669.07 mA WCDMA B4 HSDPA CH1412 @23.22dBm 543.58 mA WCDMA B4 HSUPA CH1412 @23.2dBm 579.04 mA WCDMA B5 HSDPA CH4407 @23.4dBm 553.84 mA WCDMA B5 HSUPA CH4407 @23.3dBm 558.13 mA LTE-FDD B2 CH900 @23.3dBm 748.15 mA LTE-FDD B4 CH2175 @23.4dBm 652.72 mA LTE-FDD B5 CH2525 @22.
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LTE-A Module Series EG18 Hardware Design 6.5. RF Output Power The following table shows the RF output power of EG18. Table 43: RF Output Power Frequency Max. Min. WCDMA bands 24dBm+1/-3dB <-50dBm LTE FDD bands 23dBm±2dB <-40dBm LTE TDD bands 23dBm±2dB <-40dBm 6.6. RF Receiving Sensitivity The following tables show conducted RF receiving sensitivity of EG18 module. 6.6.1.
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LTE-A Module Series EG18 Hardware Design LTE-FDD B20 (10M) -98.7dBm -98.8dBm -102.2dBm -93.3dBm LTE-FDD B28 (10M) -99.7dBm -99.7dBm -102.7dBm -94.8dBm LTE-TDD B38 (10M) -98.2dBm -98.5dBm -100.7dBm -96.3dBm LTE-TDD B40 (10M) -98.2dBm -98.9dBm -100.7dBm -96.3dBm LTE-TDD B41 (10M) -97.2dBm -97.4dBm -99.7dBm -94.3dBm 6.6.2. EG18-NA Receiving Sensitivity Table 45: EG18-NA Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 1) 3GPP (SIMO) WCDMA B2 -110dBm -109.
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LTE-A Module Series EG18 Hardware Design NOTES 1) SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which can improve Rx performance. 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is important to refer ESD handling precautions applying ESD sensitive components.
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LTE-A Module Series EG18 Hardware Design  The heatsink should be designed with as many fins as possible to increase heat dissipation area. Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and module/PCB. The following figures manifest two kinds of heatsink designs for reference. Please choose one or both of them according to particular application structure.
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LTE-A Module Series EG18 Hardware Design In order to protect the components from damage, the thermal design should be optimized to guarantee that the module’s internal temperature maintains below 105°C constantly. AT+QTEMP command can be used to obtain the module’s internal temperature. As shown in the figure below.
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LTE-A Module Series EG18 Hardware Design The following figure shows the corresponding position of the eight temperature sensors of the EG18. Figure 48: Temperature Sensor Distribution NOTES 1. 2. Make sure that the PCB design provides sufficient cooling solutions for the module: proper mounting, heatsinks, and active cooling may be required depending on the integrated application. For more detailed guidelines on thermal design, please refer to document [8].
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LTE-A Module Series EG18 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and dimensional tolerances are ±0.05mm unless otherwise specified. 7.1.
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LTE-A Module Series EG18 Hardware Design Figure 50: Module Bottom Dimensions (Top View, Unit: mm) EG18_Hardware_Design 94 / 104
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LTE-A Module Series EG18 Hardware Design 7.2. Recommended Footprint Figure 51: Recommended Footprint (Top View, Unit: mm) NOTE For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB.
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LTE-A Module Series EG18 Hardware Design 7.3. Top and Bottom Views of the Module Figure 52: Top View of the Module Figure 53: Bottom View of the Module NOTE These are rendering images of EG18. For authentic appearance, please refer to the module received from Quectel.
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LTE-A Module Series EG18 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EG18 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10% RH. 3.
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LTE-A Module Series EG18 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module should be 0.13-0.15mm. For more details, please refer to document [5].
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LTE-A Module Series EG18 Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging EG18 is packaged in tape and reel carriers. Each reel is 10.56m long and contains 200 modules. The figures below show the packaging details, measured in mm.
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LTE-A Module Series EG18 Hardware Design Figure 56: Reel Specifications (Unit: mm) EG18_Hardware_Design 100 / 104
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LTE-A Module Series EG18 Hardware Design 9 Appendix A References Table 48: Related Documents SN Document Name Remark [1] Quectel_EG18_CA_Feature EG18 CA features. [2] Quectel_UMTS<E_EVB_R2.0_User_Guide EVB R2.0 user guide of UMTS and LTE modules. [3] Quectel_EM12&EG12&EG18_AT_Commands_Manual AT commands manual for EM12, EG12 and EG18 modules. [4] Quectel_EM12&EG12&EG18_GNSS_Application_Note GNSS application note for EM12, EG12 and EG18 modules.
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LTE-A Module Series EG18 Hardware Design CS Coding Scheme CSD Circuit Switched Data CTS Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air DL Downlink DRX Discontinuous Reception DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge ESR Equivalent Series Resistance FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite Syst
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LTE-A Module Series EG18 Hardware Design MO Mobile Originated MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor MS Mobile Station MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media Independent Interface SIMO Single Input Multi
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LTE-A Module Series EG18 Hardware Design VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Val
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LTE-A Module Series EG18 Hardware Design OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
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LTE-A Module Series EG18 Hardware Design re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.
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LTE-A Module Series EG18 Hardware Design This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
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LTE-A Module Series EG18 Hardware Design Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
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LTE-A Module Series EG18 Hardware Design 2) Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplémentaires sur l'émetteur ne seront pas nécessaires. Toutefois, l'intégrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformité supplémentaires requis pour ce module installé.
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LTE-A Module Series EG18 Hardware Design L'intégrateur OEM doit être conscient de ne pas fournir des informations à l'utilisateur final quant à la façon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intègre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations réglementaires requises et avertissements comme indiqué dans ce manuel.