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AG525R-GL QuecOpen

Hardware Design

Automotive Module Series

Version: 1.0.0

Date: 2020-10-13

Status: Preliminary

www.quectel.com

Summary of content (107 pages)

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AG525R-GL QuecOpen Hardware Design Automotive Module Series Version: 1.0.0 Date: 2020-10-13 Status: Preliminary www.quectel.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Copyright The information contained here is proprietary technical information of Quectel Wireless Solutions Co., Ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright © Quectel Wireless Solutions Co., Ltd.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design About the Document Revision History Version - 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Contents About the Document ................................................................................................................................ 3 Contents .................................................................................................................................................... 4 Table Index ........................................................................................................................
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.13. 3.14. 3.15. 3.16. 3.17. 3.18. 3.19. SDIO Interface ........................................................................................................................ 58 SPI Interfaces ......................................................................................................................... 60 RGMII Interface .................................................................................................................
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table Index Table 1: Frequency Bands of AG525R-GL QuecOpen® Module .............................................................. 14 Table 2: Key Features ............................................................................................................................. 17 Table 3: I/O Parameters Definition...........................................................................................................
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 42: GPRS Multi-slot Classes........................................................................................................ 104 Table 43: EDGE Modulation and Coding Schemes ...............................................................................
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure Index Figure 1: Functional Diagram for AG525R-GL QuecOpen®..................................................................... 20 Figure 2: Pin Assignment (Top View) ....................................................................................................... 22 Figure 3: Sleep Mode Current Consumption Diagram.............................................................................
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 42: Top View of the Module .......................................................................................................... 94 Figure 43: Bottom View of the Module .................................................................................................... 94 Figure 44: Recommended Reflow Soldering Thermal Profile .................................................................. 96 Figure 45: Tape Specifications..........
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 1 Introduction QuecOpen® is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the advantages of QuecOpen® solution. Especially, its advantage in reducing the product cost is greatly valued by customers.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design ❒WCDMA IV/ LTE Band 4/66:≤5.000dBi ❒WCDMA V/ LTE Band 5:≤9.416dBi ❒LTE Band 12:≤8.734dBi ❒LTE Band 13:≤9.173dBi ❒LTE Band 26:≤9.337dBi ❒LTE Band 71:≤8.447dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design IRSS-GEN "This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 2 Product Concept 2.1. General Description AG525R-GL QuecOpen module is a baseband processor platform based on ARM Cortex A7 kernel. The maximum dominant frequency is up to 1.497 GHz. AG525R-GL QuecOpen module is a series of automotive-grade LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication modules with receive diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA, EDGE and GPRS networks.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design B21+B28 B25+B25/B26 B28+B38/B40/B41/B28 B29+B30/B66 B2+B12/B13/B29/B2/B30/B4/B5/B66/B71/B7 B30+B66 B34+B41 B38+B38 B39+B41/B39 B3+B18/B19/B20/B28/B38/B3/B40/B41/B5/B7/B8 B40+B40 B41+B41 B4+B12/B13/B29/B30/B4/B5/B71/B7 B5+B25/B30/B38/B40/B41/B5/B66/B7 B66+B66/B71 B7+B12/B20/B28/B32/B66/B7/B8 B8+B11/B32/B38/B39/B40/B41/B8 3CA (DL) B12+B66+B66 B12+B12+B66 B13+B66+B66 B1+B1+B28/B3/B5/B7/B41/B8 B1+B3+B18/B19/B20/B28/B38/B3/B40/B41/B5/B7/B8 B1+B40+B40
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Automotive Module Series AG525R-GL QuecOpen Hardware Design B39+B41+B4 B39+B39+B41 B3+B28+B40/B41 B3+B3+B20/B28/B41/B7/B8/B38/B40/B5 B3+B40+B40 B3+B41+B41 B3+B5+B40/B7 B3+B7+B20/B28/B7/B8 B3+B8+B38/B40 B40+B40+B40 B41+B41+B41 B4+B12+B12/B30 B4+B29+B30 B4+B4+B12/B13/B29/B30/B5/B71/B7 B4+B5+B30/B5 B4+B7+B12/B7 B5+B30+B66 B5+B40+B40 B5+B5+B66/B30 B5+B66+B66 B5+B7+B7 B66+B66+B66/B71 B7+B12+B66/B12 B7+B20+B32 B7+B66+B66 B7+B7+B8/B28/B20/B66 B8+B39+B39 B8+B40+B40 B8+B41+B41 B8+B8+B39/B41 WCDMA (with Rx-diversity
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 2.2. Key Features The following table describes detailed features of the module. Table 2: Key Features Feature Details Power Supply VBAT_BB/VBAT_RF:  Supply voltage: 3.3–4.3 V  Typical supply voltage: 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Text and PDU modes Point to point MO and MT SMS cell broadcast SMS storage: ME by default SMS     (U)SIM Interfaces Support USIM/SIM card: 1.8/3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Rx-diversity Support LTE/WCDMA Rx-diversity Antenna Interfaces   Main antenna interface (ANT_MAIN) Rx-diversity antenna interface (ANT_DIV) Physical Characteristics   Dimensions: (38.0 ±0.2) mm × (42.0 ±0.2) mm × (2.65 ±0.2) mm Weight: approx. 9.
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ANT_DIV ANT_MAIN Automotive Module Series AG525R-GL QuecOpen Hardware Design Diplexer Diplexer VBAT_RF 2G PA+DP16T ... Duplexers, SAWs and Qualplexers ... QDM-M/HB QDM-LB ... QLNA*2 ... APT ... MMPA ... NAND LPDDR4X Transceiver VBAT_BB QLINK PMIC Control Control Baseband PWRKEY RESET ADC×3 38.4M XO PCM I2S PCIe USB2.0/3.0 RGMII SPI x2 UART×3 I2C SDIO (U)SIM GPIOs x2 Figure 1: Functional Diagram for AG525R-GL QuecOpen® 2.4.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3 Application Interfaces 3.1. General Description The module is designed with 400 LGA pins that can be connected to cellular application platforms. Module interfaces are described in detail in the following sub-chapters:             Power supply (U)SIM interfaces USB 2.0/3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 136 200 RESERVED 135 ADC2 139 142 RESERVED GND 145 GND 148 GND 151 154 RESERVED 157 RESERVED GND 160 163 RESERVED 166 RESERVED IMU_INT1 169 GND 172 175 RESERVED 178 RESERVED 181 IMU_PWR_EN 184 RESERVED IMU_INT2 187 190 RESERVED 202 RESERVED GND 193 196 201 RESERVED RESERVED GND 134 GND RESERVED 290 133 RESERVED 291 RESERVED 292 RESERVED 293 RESERVED 294 RESERVED 295 RESERVED 296 RESE
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Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTES 1. 2. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition of the module and the alternate functions of multiplexing pins.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 4: Pin Description Power Supply I/O Description DC Characteristics Comment VBAT_BB 241, 242, 244 PI Power supply for the module’s baseband part Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V It must be provided with sufficient current up to 0.8 A. VBAT_RF 109, 111, 112, 114 PI Power supply for the module’s RF part Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V It must be provided with sufficient current up to 2 A. Vnorm = 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design For 3.0 V (U)SIM: Vmax = 3.05 V Vmin = 2.7 V For 1.8 V (U)SIM: VILmax = 0.36 V VIHmin = 1.26 V VOLmax = 0.4 V VOHmin = 1.44 V USIM1_DATA 254 IO (U)SIM1 card data For 3.0 V (U)SIM: VILmax = 0.57 V VIHmin = 2.0 V VOLmax = 0.4 V VOHmin = 2.28 V USIM1_CLK 253 DO (U)SIM1 card clock For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V For 3.0 V (U)SIM: VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design VIHmin = 1.26 V VOLmax = 0.4 V VOHmin = 1.44 V For 3.0 V (U)SIM: VILmax = 0.57 V VIHmin = 2.0 V VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V USIM2_CLK 259 DO (U)SIM2 card clock For 3.0 V (U)SIM: VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V USIM2_RST 260 DO (U)SIM2 card reset For 3.0 V (U)SIM: VOLmax = 0.4 V VOHmin = 2.28 V If unused, keep it open. VILmin = -0.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design transmit (-) USB_SS_RX_ P 90 AI USB 3.0 super-speed receive (+) USB_SS_RX_ M 88 AI USB 3.0 super-speed receive (-) Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design send VOHmin = 1.35 V UART1_RTS 74 DI UART1 request to send VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V UART1_TXD 70 DO UART1 transmit VOLmax = 0.45 V VOHmin = 1.35 V 72 DI UART1 receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V Pin Name Pin No. I/O Description DC Characteristics BT_UART_TXD 59 DO BT UART transmit VOLmax = 0.45 V VOHmin = 1.35 V BT UART receive VILmin = -0.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design I2C1_SDA 80 OD resistor is required. 1.8 V only. Can be configured to GPIO. If unused, keep them open. I2C1 serial data I2S Interface (for Codec Configuration by Default) Pin Name Pin No. I/O Description DC Characteristics CDC_RST 77 DO Codec reset VOLmax = 0.45 V VOHmin = 1.35 V I2S_MCLK 81 DO Clock output for codec VOLmax = 0.45 V VOHmin = 1.35 V I2S_WS 73 IO I2S word select VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design PCM_IN 263 DI PCM data input VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V PCM_OUT 261 DO PCM data output VOLmax = 0.45 V VOHmin = 1.35 V Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 14 DI RGMII receive data bit 1 RGMII_CTL_RX 15 DI RGMII receive control RGMII_RX_2 16 DI RGMII receive data bit 2 RGMII_RX_3 17 DI RGMII receive data bit 3 RGMII_CK_RX 19 DI RGMII receive clock RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3
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Automotive Module Series AG525R-GL QuecOpen Hardware Design SDC1_DATA_0 49 IO SDIO data bit 0 SDC1_DATA_1 50 IO SDIO data bit 1 SDC1_DATA_2 51 IO SDIO data bit 2 SDC1_DATA_3 52 IO SDIO data bit 3 SDC1_CMD 48 IO SDIO command SDC1_DATA_4 53 IO SDIO data bit 4 SDC1_DATA_5 55 IO SDIO data bit 5 SDC1_DATA_6 56 IO SDIO data bit 6 SDC1_DATA_7 58 IO SDIO data bit 7 VOLmax = 0.45 V VOHmin = 1.4 V VILmin = -0.3 V VILmax = 0.58 V VIHmin = 1.27 V VIHmax = 2.0 V VOLmax = 0.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design SPI2_CS 105 DO SPI2 chip select VOLmax = 0.45 V VOHmin = 1.35 V SPI2_MISO 106 DI SPI2 master-in salve-out VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V SPI2_MOSI 108 DO SPI2 master-out slave-in VOLmax = 0.45 V VOHmin = 1.35 V ADC Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 247 AI General-purpose ADC interface Voltage Range: 0–1.875 V If unused, keep it open.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WLAN_PWR_ EN2 225 DO WLAN power supply enable control 2 VOLmax = 0.45 V VOHmin = 1.35 V WLAN_PWR_ EN1 222 DO WLAN power supply enable control 1 VOLmax = 0.45 V VOHmin = 1.35 V WLAN_EN 228 DO WLAN enable VOLmax = 0.45 V VOHmin = 1.35 V DI LTE&WLAN/BT coexistence receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 5: Alternate Functions of Multiplexing Pins Pin No. Pin Name 27 RGMII_PWR_EN 29 RGMII_INT 31 Default Function Reset 1) Wake up Interrupt 2) Power Domain BS-PD, L Y 1.8 V BS-PD, L Y 1.8 V RGMII_RST BS-PD, L Y 1.8 V 30 PCIE_WAKE BS-PD, L Y 1.8 V 36 PCIE_CLKREQ BS-PD, L Y 1.8 V 39 PCIE_RST BS-PD, L Y 1.8 V 45 EMMC_PWR_EN BS-PD, L Y 1.8 V 53 SDC1_DATA_4 BSH-PD, L N 1.8 V 54 EMMC_RST BS-PD, L Y 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 71 UART1_CTS GPIO_23 BS-PD, L N 1.8 V 72 UART1_RXD GPIO_21 BS-PU, L Y 1.8 V 74 UART1_RTS GPIO_22 BS-PD, L Y 1.8 V 107 DBG_TXD BS-PD, L N 1.8 V 110 DBG_RXD BS-PD, L Y 1.8 V 265 PCM_SYNC 262 PCM_CLK I2S_WS GPIO_12 BS-PD, L Y 1.8 V I2S_SCK GPIO_15 BS-PD, L Y 1.8 V PCM 263 PCM_IN I2S_DIN GPIO_13 BS-PD, L Y 1.8 V 261 PCM_OUT I2S_DOUT GPIO_14 BS-PD, L Y 1.8 V 77 CDC_RST GPIO_86 BS-PD, L Y 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 259 USIM2_CLK BSH-PD, L N 1.8/2.85 V 257 USIM2_DATA BSH-PD, L N 1.8/2.85 V 258 USIM2_DET BS-PD, L Y 1.8 V 210 SPI1_MOSI GPIO_72 BS-PD, L N 1.8 V 213 SPI1_CS GPIO_74 BS-PD, L N 1.8 V 216 SPI1_CLK GPIO_75 BS-PD, L Y 1.8 V 219 SPI1_MISO GPIO_73 BS-PD, L N 1.8 V SPI 108 SPI2_MOSI GPIO_4 BS-PD, L N 1.8 V 105 SPI2_CS GPIO_6 BS-PD, L Y 1.8 V 103 SPI2_CLK GPIO_7 BS-PD, L N 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 102 GPIO3 BS-PD, L N 1.8 V 104 GPIO4 BS-PD, L N 1.8 V 116 GPIO5 BS-PD, L N 1.8 V 243 GPIO6 BS-PD, L N 1.8 V 246 GPIO7 BS-PD, L Y 1.8 V 249 GPIO8 L N 1.8 V 264 GPIO9 BS-PD, L Y 1.8 V 267 GPIO10 BS-PD, L N 1.8 V 289 GPIO11 BS-PD, L Y 1.8 V GPIO NOTES 1. “Alternate Function 1/2” takes effect only after software configuration. 2. 1) See Table 4 for more details about the symbol description. 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 6: Overview of Operating Modes Mode Details Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 3: Sleep Mode Current Consumption Diagram NOTE DRX cycle index values are broadcasted by the base station through the wireless network. 3.5.1.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter sleep mode.    Use sleep API to enable the sleep mode.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design   Sending data to the module through USB will wake up the module. When the module has URC to report, it will send remote wake-up signals via USB bus so as to wake up the host. 3.5.1.2. USB Application without USB Remote Wakeup Function If the host supports USB suspend/resume, but does not support remote wake-up function, it needs to be woken up via the module’s GPIO. There are three preconditions to let the module enter sleep mode.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design The following figure shows the connection between the module and the host. Figure 6: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. 3.5.2.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 7: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_BB 241, 242, 244 Power supply for the module’s baseband part 3.3 3.8 4.3 V VBAT_RF 109, 111, 112, 114 Power supply for the module’s RF part 3.3 3.8 4.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design DC_3V8 VBAT_BB VBAT_RF D1 C1 + 100 µF C2 100 nF C3 C5 + C6 C4 C7 C8 33 pF 10 pF 100 µF 100 nF 33 pF 10 pF Module Figure 8: VBAT Reference Design 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. If the voltage drop between the input and output is not too high, it is recommended to use an LDO to supply power for the module.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.6.4. Monitor the Power Supply API can be used to monitor the VBAT_BB voltage value. For more details, see document [2]. 3.7. Power on and off Scenarios 3.7.1. Turn on Module with PWRKEY Table 8: PWRKEY Pin Description Pin Name PWRKEY Pin No. 7 Description DC Characteristics Comment Turn on/off the module VIHmax = 1.89 V VIHmin = 1.17 V VILmax = 0.63 V 1.8 V power domain. Pulled-up internally. Active low.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 11: Turn on the Module Using Keystroke The power on scenario is illustrated in the following figure. Figure 12: Power-on Timing NOTES 1. 2. Please make sure that VBAT is stable for at least 30 ms before pulling down PWRKEY pin. It is recommended to use an external OD/OC circuit to control the PWRKEY pin.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.7.2. Turn on Module with PON_1 Table 9: PON_1 Pin Description Pin Name Pin No. Description Comment PON_1 248 Driving it high will turn on the module automatically Valid trigger range: 0.78 V~1.89 V. When the module is powered off, drive PON_1 high for at least 500 ms will turn on the module automatically. A simple reference circuit is illustrated in the following figure. PON_1 10K 0.78–1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design VBA T ≥ 2 s TBD PWRKEY Module Status RUNNING Power- down procedure OFF VDD_ EXT Figure 14: Power-off Timing 3.7.3.2. Turn off Module Using API Interface It is also a safe way to use API interface to turn off the module, which is similar to turning off the module via PWRKEY Pin. See document [2] for details about API function. NOTES 1. 2.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 10: RESET Pin Description Pin Name RESET Pin No. 8 Description DC Characteristics Reset the module VIHmax = 1.89 V VIHmin = 1.17 V VILmax = 0.63 V Comment The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET. RESET 370–620 ms 4.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 17: Timing of Resetting Module NOTE Please assure that there is no large capacitance on PWRKEY and RESET pins. 3.9. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM cards are supported. Table 11: Pin Definition of (U)SIM Interface Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design USIM2_DET 258 DI (U)SIM2 card hot-plug detect The module supports (U)SIM card hot-plug via the USIM_DET pin and either low level or high level detection is supported. The function is disabled by default and can be enabled by AT+QSIMDET. See document [3] for more details of the command. The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design To enhance the reliability and availability of the (U)SIM card, follow the criteria below in the (U)SIM circuit design:       Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the trace between the ground of the module and that of the (U)SIM card connector short and wide.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design standard specification. Require differential impedance of 90 Ω. USB_DM 87 AI/AO USB differential data bus (-) USB_SS_TX_P 93 AO USB 3.0 super-speed transmit (+) USB_SS_TX_M 91 AO USB 3.0 super-speed transmit (-) USB_SS_RX_P 90 AI USB 3.0 super-speed receive (+) USB_SS_RX_M 88 AI USB 3.0 super-speed receive (-) Compliant with USB 3.0 standard specification. Require differential impedance of 90 Ω.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design To ensure signal integrity of USB data lines, components R1, R2 and L1 must be placed close to the module, and also these resistors should be placed close to each other. The capacitors C1 and C2 should be placed near the module. The capacitors C3 and C4 should be placed near the AP. The extra stubs of trace must be as short as possible. The following principles of USB interface should be complied with, so as to meet USB 2.0 and USB 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 13: Pin Definition of UART1 Interface Pin Name Pin No. I/O Description Comment UART1_CTS 71 DO UART1 clear to send UART1_RTS 74 DI UART1 request to send UART1_TXD 70 DO UART1 transmit UART1_RXD 72 DI UART1 receive 1.8 V power domain. Can be configured to GPIOs. Table 14: Pin Definition of BT UART Interface Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design The module provides 1.8 V UART interfaces. A level translator should be used if customers’ application is equipped with a 3.3 V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments (visit http://www.ti.com for more information) is recommended. The following figure shows a reference design. Figure 22: Reference Circuit with Translator Chip Another example with transistor translation circuit is shown as below.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.12. I2S and I2C Interfaces The module provides I2S and I2C interfaces for audio function design. Table 17: Pin Definition of I2S Interface Pin Name Pin No. I/O Description CDC_RST 77 DO Codec reset I2S_MCLK 81 DO Clock output for codec I2S_WS 73 IO I2S word select I2S_SCK 75 DO I2S clock I2S_DIN 76 DI I2S data in I2S_DOUT 78 DO I2S data out Comment 1.8 V power domain. Can be configured to GPIOs.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTE The module works as a master device pertaining to I2C interface. 3.13. SDIO Interface The module provides an SDIO interface. It is recommended to use the interface for eMMC application. Table 19: Pin Definition of SDIO Interface Pin Name Pin No. I/O Description Comment SDIO_VDD 60 PI SDIO power supply Connect it to VDD_EXT.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design The following is a reference design of SDIO interface for eMMC application. VDD_1V8 R12 NM R13 NM R14 NM R15 NM R16 NM R17 NM R18 NM R19 NM R20 10K R21 47K VDD_1.8V SDC1_DATA_0 SDC1_DATA_1 SDC1_DATA_2 SDC1_DATA_3 SDC1_DATA_4 SDC1_DATA_5 SDC1_DATA_6 SDC1_DATA_7 SDC1_CMD SDC1_CLK EMMC_RST EMMC_PWR_EN SDIO_VDD R1 0R DAT0 R2 0R VCCQ C12 100 nF DAT1 R3 0R DAT2 R4 0R VDD_3V DAT3 R5 0R VCC C14 100 nF DAT4 R6 0R C13 1 µF C15 2.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.14. SPI Interfaces The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of SPI is up to 50 MHz. Table 20: Pin Definition of SPI Interfaces Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 21: Parameters of SPI Interface Timing Parameter Description Min. Typ. Max. Unit T SPI clock period 20.0 - - ns t(ch) SPI clock high-level time 9.0 - - ns t(cl) SPI clock low-level time 9.0 - - ns t(mov) SPI master data output valid time -5.0 - 5.0 ns t(mis) SPI master data input setup time 5.0 - - ns t(mih) SPI master data input hold time 1.0 - - ns NOTE The module provides a 1.8 V SPI interface.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design RGMII_CTL_RX 15 DI RGMII receive control RGMII_RX_2 16 DI RGMII receive data bit 2 RGMII_RX_3 17 DI RGMII receive data bit 3 RGMII_CK_RX 19 DI RGMII receive clock RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bi
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Automotive Module Series AG525R-GL QuecOpen Hardware Design The following figure shows a reference design of RGMII interface with PHY application. Figure 28: Reference Circuit of RGMII Interface with PHY Application In order to enhance the reliability and availability of customers’ application, please follow the criteria below in the Ethernet PHY circuit design:          The I/O voltage of RGMII matches with that of PHY.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design   Spacing to all other signals is larger than three times of line width. Resistors R7–R12 should be placed near the module. Resistor R1–R6 should be placed near the Ethernet PHY. The value of R1–R16 varies with the selection of PHY. 3.16. WLAN and BT Interfaces* The module provides a PCIe interface for WLAN function and UART & PCM interfaces for BT function. Table 23: Pin Definition of WLAN and BT Interfaces Pin Name Pin No.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 1.8 V power domain. Can be configured to GPIOs.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design VDD_EXT R1 100K R2 100K PCIE_CLKREQ PCIE_CLKREQ_N PCIE_WAKE PCIE_WAKE PCIE_RST PCIE_RST PCIE_REFCLK_P PCIE_REFCLKP PCIE_REFCLKM PCIE_REFCLK_M PCIE_TX_M PCIE_TX_P C1 100 nF PCIE_RXM C2 100 nF PCIE_RXP C3 100 nF PCIE_RX_M C4 100 nF PCIE_RX_P PCIE_TXM PCIE_TXP COEX_UART_ RXD COEX_UART_ TXD COEX_UART_ TXD COEX_UART_ RXD BT_UART_TXD BT_UART_RXD BT_UART_RXD BT_UART_TXD BT_UART_RTS BT_UART_RTS BT_UART_CTS BT_UART_CTS PCM_SYN
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Automotive Module Series AG525R-GL QuecOpen Hardware Design The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications.      It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the differential impedance is 95 Ω ±10%.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design ADC0 Voltage Range 0 1.875 V ADC1 Voltage Range 0 1.875 V ADC2 Voltage Range 0 1.875 V ADC Resolution 14 bits ADC Sample Rate 4.8 MHz NOTES 1. 2. 3. The input voltage for each ADC interface must not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pins when VBAT is removed. It is recommended to use resistor divider circuit for ADC application. 3.18.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.19. GPIO Interfaces The module provides 11 GPIOs. Table 27: Pin Definition of GPIOs Pin Name Pin No. I/O GPIO1 100 IO GPIO2 101 IO GPIO3 102 IO GPIO4 104 IO GPIO5 116 IO GPIO6 243 IO GPIO7 246 IO GPIO8 249 DO GPIO9 264 IO GPIO10 267 IO GPIO11 289 IO Description Comment General-purpose input/output 1.8 V power domain. If unused, keep them open.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 4 Antenna Interfaces The module includes one main antenna interface (ANT_MAIN) and one Rx-diversity antenna interface (ANT_DIV) which is used to resist the fall of signals caused by high speed movement and multipath effect. The antenna ports have an impedance of 50 Ω. 4.1. Main/Rx-diversity Antenna Interface 4.1.1. Pin Definition The pin definition of Main/Rx-diversity antenna interfaces are shown below.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B3 1710–1785 1805–1880 MHz WCDMA B4 1710–1755 2110–2155 MHz WCDMA B5 824–849 869–894 MHz WCDMA B8 880–915 925–960 MHz WCDMA B9 1749.9–1784.9 1844.9–1879.9 MHz WCDMA B19 830–845 875–890 MHz LTE-FDD B1 1920–1980 2110–2170 MHz LTE-FDD B2 1850–1910 1930–1990 MHz LTE-FDD B5 824–849 869–894 MHz LTE-FDD B7 2500–2570 2620–2690 MHz LTE-FDD B8 880–915 925–960 MHz LTE-FDD B9 1749.9–1784.9 1844.9–1879.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B32 1) 1452–1496 MHz LTE-TDD B34 2010–2025 2010–2025 MHz LTE-TDD B38 2570–2620 2570–2620 MHz LTE-TDD B39 1880–1920 1880–1920 MHz LTE-TDD B40 2300–2400 2300–2400 MHz LTE-TDD B41 2555–2655 2555–2655 MHz LTE-TDD B66 1710–1780 2110–2200 MHz LTE-TDD B71 663–698 617–652 MHz NOTE 1) LTE-FDD B29, B30 and B32 support Rx only. 4.1.3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTES ANT_DIV function is enabled by default. AT+QCFG="diversity",0 command can be used to disable receive diversity. See document [3] for details of the command. 4.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design:       Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 4.2. Antenna Installation 4.2.1. Antenna Requirements The following table shows the requirements on the main antenna and the Rx-diversity antenna. Table 30: Antenna Requirements Type Requirements GSM/UMTS/LTE VSWR: ≤ 2 Efficiency: > 30% Max input power: 50 W Input impedance: 50 Ω Cable insertion loss: < 1 dB (GSM850, EGSM900, WCDMA B5/B8/B19, LTE-FDD B5/B8/B9/B12/B13/B17/B18/B19/B20/B26/B28/B29/B71) Cable insertion loss: < 1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 4.2.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the HFM connector provided by Rosenberger. Figure 36: Description of the HFM Connector For more details, visit https://www.rosenbergerap.com.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 5 Reliability, Radio and Electrical Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 31: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 6.0 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 2.0 A Voltage at Digital Pins -0.3 2.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.2. Power Supply Ratings Table 32: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF The actual input voltages must be kept between the minimum and maximum values. 3.3 3.8 4.3 V USB_VBUS USB connection detection 3.0 5.0 5.25 V 5.3. Operation and Storage Temperatures Table 33: Operation and Storage Temperatures Parameter Min. Typ. Max.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.4. Current Consumption Table 34: Module Current Consumption (25 °C, 3.8 V Power Supply) Description Conditions Typ. Unit OFF state Power down 0.021 mA AT+CFUN=0 (USB disconnected) 1.144 mA GSM850 DRX = 2 (USB disconnected) 3.183 mA GSM850 DRX = 5 (USB disconnected) 2.128 mA GSM850 DRX = 5 (USB suspend) TBD mA GSM850 DRX = 9 (USB disconnected) 1.760 mA EGSM900 DRX = 2 (USB disconnected) 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA PF = 256 (USB disconnected) 2.019 mA WCDMA PF = 512 (USB disconnected) 1.925 mA LTE-FDD PF = 32 (USB disconnected) 4.123 mA LTE-FDD PF = 64 (USB disconnected) 2.968 mA LTE-FDD PF = 64 (USB suspend) TBD mA LTE-FDD PF = 128 (USB disconnected) 3.208 mA LTE-FDD PF = 256 (USB disconnected) 2.541 mA LTE-TDD PF = 32 (USB disconnected) 5.170 mA LTE-TDD PF = 64 (USB disconnected) 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design EDGE data transfer (GNSS OFF) EGSM900 3DL/2UL @ 32 dBm 518.5 mA EGSM900 2DL/3UL @ 30dBm 618.1 mA EGSM900 1DL/4UL @ 29 dBm 690.5 mA DCS1800 4DL/1UL @ 29.5 dBm 236.8 mA DCS1800 3DL/2UL @ 29.0dBm 367.6 mA DCS1800 2DL/3UL @ 26.5 dBm 426.2 mA DCS1800 1DL/4UL @ 25.5 dBm 501.9 mA PCS1900 4DL/1UL @ 29.5 dBm 229.9 mA PCS1900 3DL/2UL @ 29.0dBm 362.5 mA PCS1900 2DL/3UL @ 26.5 dBm 412.4 mA PCS1900 1DL/4UL @ 25.5 dBm 469.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) PCS1900 2DL/3UL @ 23.0dBm 322.2 mA PCS1900 1DL/4UL @ 22.0dBm 371.2 mA WCDMA B1 HSDPA @ 23.0 dBm 590.7 mA WCDMA B2 HSDPA @ 23.0 dBm 656.7 mA WCDMA B3 HSDPA @ 23.0 dBm 610.42 mA WCDMA B4 HSDPA @ 23.0 dBm 650.27 mA WCDMA B5 HSDPA @ 23.0 dBm 588.94 mA WCDMA B8 HSDPA @ 23.0 dBm 621.63 mA WCDMA B9 HSDPA @ 23.0 dBm 613.25 mA WCDMA B19 HSDPA @ 23.0 dBm 618.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design GSM voice call LTE-FDD B9 @ 23.0dBm 597.53 mA LTE-FDD B11 @ 23.0dBm 674.67 mA LTE-FDD B12 @ 23.0dBm 595.3 mA LTE-FDD B13 @ 23.0dBm 661.65 mA LTE-FDD B17 @ 23.0dBm 596.13 mA LTE-FDD B18 @ 23.0dBm 636.57 mA LTE-FDD B19 @ 23.0dBm 627.77 mA LTE-FDD B20 @ 23.0dBm 617.46 mA LTE-FDD B21 @ 23.0dBm 665.74 mA LTE-FDD B25 @ 23.0dBm 622.94 mA LTE-FDD B26 @ 23.0dBm 623.07 mA LTE-FDD B28 @ 23.0dBm 597.96 mA LTE-FDD B30 @ 23.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design EGSM900, PCL = 19 @ 5.0dBm 125.1 mA DCS1800, PCL = 0 @ 30 dBm 248.9 mA DCS1800, PCL = 7 @ 16.0dBm 139.2 mA DCS1800, PCL = 15 @ 0dBm 132 mA PCS1900, PCL = 0 @ 30 dBm 255.6 mA PCS1900, PCL = 7 @ 16.0dBm 138.8 mA PCS1900, PCL = 15 @ 0dBm 129.8 mA WCDMA B1 @ 22.5 dBm 620.63 mA WCDMA B2 @ 22.5 dBm 666.99 mA WCDMA B3 @ 22.5 dBm 623 mA WCDMA B4 @ 22.5 dBm 659.48 mA WCDMA B5 @ 22.5 dBm 612.57 mA WCDMA B8 @ 23.0dBm 615.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B1 24dBm +1/-3 dB < -49 dBm WCDMA B2 24dBm +1/-3 dB < -49 dBm WCDMA B3 24dBm +1/-3 dB < -49 dBm WCDMA B4 24dBm +1/-3 dB < -49 dBm WCDMA B5 24dBm +1/-3 dB < -49 dBm WCDMA B8 24dBm +1/-3 dB < -49 dBm WCDMA B9 24dBm +1/-3 dB < -49 dBm WCDMA B19 24dBm +1/-3 dB < -49 dBm LTE-FDD B1 23 dBm ±2 dB < -39 dBm LTE-FDD B2 23 dBm ±2 dB < -39 dBm LTE-FDD B3 23 dBm ±2 dB < -39 dBm LTE-FDD B4 23 dBm ±2 dB < -39 dBm LTE-FD
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Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B26 23 dBm ±2 dB < -39 dBm LTE-FDD B28 23 dBm ±2 dB < -39 dBm LTE-FDD B29 23 dBm ±2 dB < -39 dBm LTE-FDD B30 23 dBm ±2 dB < -39 dBm LTE-FDD B32 23 dBm ±2 dB < -39 dBm LTE-TDD B34 23 dBm ±2 dB < -39 dBm LTE-TDD B38 23 dBm ±2 dB < -39 dBm LTE-TDD B39 23 dBm ±2 dB < -39 dBm LTE-TDD B40 23 dBm ±2 dB < -39 dBm LTE-TDD B41 23 dBm ±2 dB < -39 dBm LTE-FDD B66 23 dBm ±2 dB < -39 dBm LTE-FDD B71 23 dBm ±2 dB < -39
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Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B1 -112 -112 -114 -106.7 WCDMA B2 -112 -112.5 -113 -106.7 WCDMA B3 -113 -113 -114.5 -106.7 WCDMA B4 -112.5 -113 -114 -106.7 WCDMA B5 -110 -113 -114.5 -106.7 WCDMA B8 -112 -113.5 -114.5 -106.7 WCDMA B9 -113.5 -112.5 -114 -103.7 WCDMA B19 -110 -113.5 -114 -103.7 LTE-FDD B1 (10 MHz) -98.6 -99.4 -102.12 -96.3 LTE-FDD B2 (10 MHz) -98.9 -98.8 -101.92 -94.3 LTE-FDD B3 (10 MHz) -99.4 -99 -102.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B26(10 MHz) -100 -100.12 -103.02 -94.3 LTE-FDD B28 (10 MHz) -100.1 -100.02 -103.32 -94.8 LTE-FDD B29 (10 MHz) -99.22 -100.22 -102.72 -93.3 LTE-FDD B30 (10 MHz) -97.82 -98.82 -101.32 -95.3 LTE-FDD B32 (10 MHz) -94.82 -96.82 -98.82 -95.3 LTE-TDD B34 (10 MHz) -97.9 -97.82 -100.92 -96.3 LTE-TDD B38 (10 MHz) -99.2 -98.12 -101.62 -96.3 LTE-TDD B39 (10 MHz) -98.3 -99.02 -101.5 -96.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.8. Thermal Consideration In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal consideration:        On customers’ PCB design, please keep placement of the module away from heating sources, especially high power components such as ARM processor, audio power amplifier, power supply, etc.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 38: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB) NOTES 1. 2. For better performance, the maximum temperature of the internal BB chip should be kept below 105 °C. When the maximum temperature of the BB chip reaches or exceeds 105 °C, the module works normal but provides reduced performance (such as RF output power and data rate).
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 6.1.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 40: Module Bottom Dimensions (Top View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 6.2. Recommended Footprint Figure 41: Recommended Footprint (Top View) NOTE For convenient maintenance of the module, please keep about 3 mm between the module and other components on the motherboard.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 6.3. Top and Bottom Views Figure 42: Top View of the Module Figure 43: Bottom View of the Module NOTE These are renderings of the module. For authentic appearance, see the module received from Quectel.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 7 Storage, Manufacturing and Packaging 7.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTE 1. 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to IPC/JEDEC J-STD-033.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 38: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150°C and 200°C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220°C) 45–70 s Max temperature 238–246 °C Cooling down slope -1.5 to -3 °C/s Reflow Cycle Max reflow cycle 1 7.3. Packaging The module is packaged in tape and reel carriers. One reel is 10.56 meters long and contains 220 modules.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 45: Tape Specifications Figure 46: Reel Specifications AG525R-GL_QuecOpen_Hardware_Design 98 / 104
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 8 Appendix A References Table 39: Related Documents SN Document Name Remark [1] Quectel_V2X&5G_EVB_User_Guide EVB User Guide for Automotive Modules [2] Quectel_AG525R-GL_QuecOpen_Developer_Guide AG525R-GL QuecOpen Developer Guide [3] Quectel_AG525R-GL_AT_Commands_Manual AG525R-GL AT Commands Manual [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_LTE_Module_Thermal_Design_Guide Thermal Design Guide f
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Automotive Module Series AG525R-GL QuecOpen Hardware Design CTS Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air DL Downlink DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge EVDO Evolution-Data Optimized FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Sh
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Automotive Module Series AG525R-GL QuecOpen Hardware Design MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol Ppp Peak Pulse Power QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIMO Single Input Multiple Output SMS Short Message Service TDD Time Divis
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Automotive Module Series AG525R-GL QuecOpen Hardware Design Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Val
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 9 Appendix B GPRS Coding Schemes Table 41: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 10 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 AG525R-GL_QuecOpen_Hardware_Design 105 / 104
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Automotive Module Series AG525R-GL QuecOpen Hardware Design 11 Appendix D EDGE Modulation and Coding Schemes Table 43: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05 kbps 18.1 kbps 36.2 kbps CS-2: GMSK / 13.4 kbps 26.8 kbps 53.6 kbps CS-3: GMSK / 15.6 kbps 31.2 kbps 62.4 kbps CS-4: GMSK / 21.4 kbps 42.8 kbps 85.6 kbps MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps MCS-2 GMSK B 11.2 kbps 22.