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LPWA Module Series

BG95 Hardware Design

BG95_Hardware_Design 1 / 88

BG95-M2 Hardware

Design

LPWA Module Series

Rev. BG95_Hardware_Design_V1.2_Preliminary20200421

Date: 2020-04-21

Status: Preliminary

Summary of content (94 pages)

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LPWA Module Series BG95 Hardware Design BG95-M2 Design Hardware LPWA Module Series Rev. BG95_Hardware_Design_V1.
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LPWA Module Series BG95 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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LPWA Module Series BG95 Hardware Design About the Document Revision History Version Date Author Description 1.0 2019-09-30 Lyndon LIU/ Garey XIE Initial Lyndon LIU/ Garey XIE 1. Updated the GNSS function into an optional feature. 2. Updated the LTE Power Class 5 to 21 dBm. 3. Added the parameters (power supply, operating frequency, output power, etc.) of BG95-M4 and BG95-M5. 4. Updated the transmitting power parameters in Table 3 and Table 40. 5.
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LPWA Module Series BG95 Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ............................................................................................................................................
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LPWA Module Series BG95 Hardware Design 3.13. 3.14. 3.15. 3.16. 3.17. 3.18. 3.19. Network Status Indication ....................................................................................................... 52 STATUS ................................................................................................................................. 53 Behaviors of MAIN_RI ............................................................................................................ 54 USB_BOOT Interface ...
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LPWA Module Series BG95 Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes ..................................................................
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LPWA Module Series BG95 Hardware Design Table Index Table 1: Version Selection for BG95 Series Modules.............................................................................. 15 Table 2: Frequency Bands and GNSS Types of BG95 Series Modules .................................................. 15 Table 3: Key Features of BG95 Series Modules ..................................................................................... 18 Table 4: Definition of I/O Parameters ......................................
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LPWA Module Series BG95 Hardware Design Table 42: Conducted RF Receiving Sensitivity of BG95-M1 ................................................................... 75 Table 43: Conducted RF Receiving Sensitivity of BG95-M2 ................................................................... 76 Table 44: Conducted RF Receiving Sensitivity of BG95-M3 ................................................................... 77 Table 45: Electrostatic Discharge Characteristics (25 ºC, 45% Relative Humidity) .........
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LPWA Module Series BG95 Hardware Design Figure Index Figure 1: Functional Diagram .................................................................................................................. 21 Figure 2: Pin Assignment (Top View) ...................................................................................................... 23 Figure 3: Sleep Mode Application via UART ...........................................................................................
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LPWA Module Series BG95 Hardware Design 1 Introduction This document defines BG95 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG95. To facilitate application designs, it also includes some reference designs for customers’ reference.
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LPWA Module Series BG95 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG95 module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals supplied with the product.
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LPWA Module Series BG95 Hardware Design 1.2. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
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LPWA Module Series BG95 Hardware Design conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations.
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LPWA Module Series BG95 Hardware Design could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules.
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LPWA Module Series BG95 Hardware Design radiation, maximum antenna gain (including cable loss) must not exceed: ❒ Catm LTE Band2/25:≤11.000dBi ❒ Catm LTE Band4/66:≤8.000dBi ❒ Catm LTE Band5/26:≤12.541dBi ❒ Catm LTE Band12/85:≤11.798dBi ❒ Catm LTE Band13:≤12.214dBi ❒ NB LTE Band2/25:≤11.000dBi ❒ NB LTE Band4/66:≤8.000dBi ❒ NB LTE Band5:≤12.541dBi ❒ NB LTE Band12/85:≤11.798dBi ❒ NB LTE Band13:≤12.214dBi ❒NB LTE Band71:≤11.
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LPWA Module Series BG95 Hardware Design 2 Product Concept 2.1. General Description BG95 is a series of embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication modules. It provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides optional GNSS and voice* 1) functionality to meet customers’ specific application demands.
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LPWA Module Series BG95 Hardware Design BG95-M2 Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/ B27/B28/B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/ B28/B66/B71/B85 Power Class 5 (21 dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Power Class 5 (21 dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Power Class 5 (21 dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Power Class 5 (21 dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Power Class 3 (23 dBm) GPS, GLONASS, BeiDou, Galileo, QZS
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LPWA Module Series BG95 Hardware Design B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 EGPRS: 850/900/1800/1900 MHz Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B27/ B28/B66/B85 BG95-MF (Planning) Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 Power Class 5 (21 dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Wi-Fi (For Positioning Only): 2.4 GHz NOTES 1. 2. 3. 4. 5.
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LPWA Module Series BG95 Hardware Design Table 3: Key Features of BG95 Series Modules Features Details BG95-M1/-M2/-N1:  Supply voltage 1): 2.6–4.8 V  Typical supply voltage: 3.3 V Power Supply BG95-M3/-M5:  Supply voltage: 3.3–4.3 V  Typical supply voltage: 3.8 V BG95-M4:  Typical supply voltage: 3.8 V Transmitting Power           Class 5 (21 dBm +1.
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LPWA Module Series BG95 Hardware Design Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage: ME by default SMS     (U)SIM Interface Support 1.8 V USIM/SIM card only PCM Interface* Support one digital audio interface: PCM interface USB Interface     Compliant with USB 2.
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LPWA Module Series BG95 Hardware Design NOTES 1. 1) For every VBAT transition/re-insertion from 0 V, the minimum power supply voltage should be higher than 2.7 V. After the module starts up normally, the minimum safety voltage is 2.6 V. In order to ensure full-function mode, the minimum power supply voltage should be higher than 2.8 V. 2. 2) Within operation temperature range, the module is 3GPP compliant. 3.
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LPWA Module Series BG95 Hardware Design Figure 1: Functional Diagram NOTES 1. eSIM function is optional. If eSIM is selected, then any external (U)SIM cannot be used. 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 3. RESET_N is connected directly to PWRKEY inside the module. 4.
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LPWA Module Series BG95 Hardware Design 3 Application Interfaces BG95 is equipped with 102 LGA pads that can be connected to various cellular application platforms. The subsequent chapters will provide detailed descriptions of the following interfaces:            Power supply PON_TRIG Interface (U)SIM interface USB interface UART interfaces PCM and I2C interfaces* Status indication interfaces USB_BOOT interface ADC interfaces GPIO interfaces* GRFC interfaces NOTE “*” means under development.
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LPWA Module Series BG95 Hardware Design 3.1. Pin Assignment GND GND ANT_MAIN GND GND RESERVED RESERVED GND GND VBAT_RF VBAT_RF RESERVED GND 62 61 60 59 58 57 56 55 54 53 52 51 50 The following figure shows the pin assignment of BG95.
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LPWA Module Series BG95 Hardware Design NOTES 1. 2. 3. 4. 5. 6. 7. ADC0 and ADC1 cannot be used simultaneously, as ADC1 is connected directly to ADC0 inside the module. The module supports use of only one ADC interface at a time: either ADC0 or ADC1. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently.
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LPWA Module Series BG95 Hardware Design Table 5: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment BG95-M1/-M2/-N1: Vmax = 4.8 V Vmin = 2.6 V Vnorm = 3.3 V VBAT_BB 32, 33 PI Power supply for the module’s baseband part BG95-M3/-M5: Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V Please refer to NOTE 1 BG95-M4: Vnorm = 3.8 V BG95-M1/-M2/-N1: Vmax = 4.8 V Vmin = 2.6 V Vnorm = 3.3 V VBAT_RF 52, 53 PI Power supply for the module’s RF part BG95-M3/-M5: Vmax = 4.
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LPWA Module Series BG95 Hardware Design 15 DI Turn on/off the module Vnorm = 1.5 V VILmax = 0.45 V PWRKEY should never be pulled down to GND permanently. Pin Name Pin No. I/O Description DC Characteristics Comment RESET_N 17 DI Reset the module Vnorm = 1.5 V VILmax = 0.45 V I/O Description DC Characteristics Comment DO Power saving mode indication VOHmin = 1.35 V VOLmax = 0.45 V 1.8 V power domain. If unused, keep this pin open. DO Module operation status indication VOHmin = 1.
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LPWA Module Series BG95 Hardware Design USIM_RST 44 DO (U)SIM card reset VOLmax = 0.45 V VOHmin = 1.35 V USIM_DATA 45 IO (U)SIM card data VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V VOLmax = 0.45 V VOHmin = 1.35 V USIM_CLK 46 DO (U)SIM card clock VOLmax = 0.45 V VOHmin = 1.35 V USIM_GND 47 (U)SIM card ground Main UART Interface Pin Name MAIN_DTR MAIN_RXD MAIN_TXD MAIN_CTS MAIN_RTS MAIN_DCD MAIN_RI Pin No.
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LPWA Module Series BG95 Hardware Design DBG_RXD DBG_TXD 22 23 DI Debug UART receive VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V DO Debug UART transmit VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. I/O Description DC Characteristics Comment GNSS UART transmit VOLmax = 0.45 V VOHmin = 1.35 V BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain. If unused, keep this pin open. VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.
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LPWA Module Series BG95 Hardware Design If unused, keep this pin open. I2C_SDA 41 OD I2C serial data (for external codec) External pull-up resistor is required. 1.8 V only. If unused, keep this pin open. Antenna Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ANT_MAIN 60 IO Main antenna interface 50 Ω impedance ANT_GNSS 49 AI GNSS antenna interface 50 Ω impedance. If unused, keep this pin open. Pin No.
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LPWA Module Series BG95 Hardware Design GPIO5 GPIO6 GPIO7 GPIO8 66 85 86 87 IO IO IO IO General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. General-purpose input/output VOLmax = 0.45 V VOHmin = 1.
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LPWA Module Series BG95 Hardware Design VIHmin = 1.2 V VIHmax = 2.0 V AP_READY* USB_BOOT PON_TRIG 19 75 When it is in low voltage level, the module can enter airplane mode. If unused, keep this pin open. DI Application processor sleep state detection VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. DI Force the module into emergency download mode VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain.
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LPWA Module Series BG95 Hardware Design NOTES 1. For every VBAT transition/re-insertion from 0 V, the minimum power supply voltage should be higher than 2.7 V. After the module starts up normally, the minimum safety voltage is 2.6 V. In order to ensure full-function mode, the minimum power supply voltage should be higher than 2.8 V. 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset.
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LPWA Module Series BG95 Hardware Design Mode Sleep Mode In this mode, the current consumption of the module will be reduced to a lower level. During this mode, the module can still receive paging message, SMS and TCP/UDP data from the network normally. Power OFF Mode In this mode, the power management unit shuts down the power supply. The software is not active. The serial interfaces are not accessible. But the operating voltage (connected to VBAT_RF and VBAT_BB) remains applied.
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LPWA Module Series BG95 Hardware Design 2. 3. The execution of AT+CFUN command will not affect GNSS function. “*” means under development. 3.4.2. Power Saving Mode (PSM) BG95 module can enter PSM to reduce its power consumption. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. So BG95 in PSM cannot immediately respond users’ requests.
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LPWA Module Series BG95 Hardware Design EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception. If e-I-DRX is supported by the network, then it can be enabled by AT+CEDRXS=1 command. NOTE Please refer to document [2] for details about AT+CEDRXS command. 3.4.4. Sleep Mode BG95 is able to reduce its current consumption to a lower value during the sleep mode. The following sub-chapters describe the power saving procedure of BG95. 3.4.4.1.
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LPWA Module Series BG95 Hardware Design NOTE “*” means under development. 3.5. Power Supply 3.5.1. Power Supply Pins BG95 provides the following four VBAT pins for connection with an external power supply. There are two separate voltage domains for VBAT.   Two VBAT_RF pins for module’s RF part. Two VBAT_BB pins for module’s baseband part. The following table shows the details of VBAT pins and ground pins. Table 7: VBAT and GND Pins Pin Name VBAT_RF Pin No.
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LPWA Module Series BG95 Hardware Design NOTE 1) For every VBAT transition/re-insertion from 0 V, the minimum power supply voltage should be higher than 2.7 V. After the module starts up normally, the minimum safety voltage is 2.6 V. In order to ensure full-function mode, the minimum power supply voltage should be higher than 2.8 V. 3.5.2. Decrease Voltage Drop  BG95-M1/-M2/-N1: The power supply range of BG95-M1/-M2/-N1 is from 2.6 V to 4.8 V.
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LPWA Module Series BG95 Hardware Design possible. The following figure shows the star structure of the power supply. VBAT R1 0R R2 0R VBAT_RF VBAT_BB + + D1 TVS C2 C1 100uF C3 C4 100nF 33pF 10pF C5 100uF C6 C7 C8 100nF 33pF 10pF Module Figure 5: Star Structure of the Power Supply 3.5.3. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. 3.6. Turn on and off Scenarios 3.6.1.
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LPWA Module Series BG95 Hardware Design Figure 6: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module Using Keystroke The power on scenario is illustrated in the following figure.
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LPWA Module Series BG95 Hardware Design Figure 8: Power-on Timing NOTES 1. Make sure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms. 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 3.6.2.
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LPWA Module Series BG95 Hardware Design 3.6.2.1. Turn off Module through PWRKEY Driving PWRKEY low for 650–1500 ms, the module will execute power-down procedure after PWRKEY is released. The power-off scenario is illustrated in the following figure. Figure 9: Power-off Timing 3.6.2.2. Turn off Module through AT Command It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the module via PWRKEY.
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LPWA Module Series BG95 Hardware Design Table 9: Pin Definition of RESET_N Pin Name RESET_N Pin No. 17 Description Reset the module DC Characteristics Comment VILmax = 0.45 V Multiplexed from PWRKEY (connected directly to PWRKEY inside the module). The reset scenario is illustrated in the following figure. VBA T ≤ 3.8 s ≥2s RESET_N Module Status VIL ≤ 0.45 V Running Resetting Restart Figure 10: Reset Timing The recommended circuit is similar to the PWRKEY control circuit.
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LPWA Module Series BG95 Hardware Design S2 RESET_N TVS Close to S2 Figure 12: Reference Circuit of RESET_N by Using Button NOTE Please assure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG Interface BG95 provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects a rising edge, the module will be woken up from PSM. Table 10: Pin Definition of PON_TRIG Interface Pin Name PON_TRIG Pin No.
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LPWA Module Series BG95 Hardware Design VDD_1V8 10K 10K PON_TRIG_EXT 100K 100K PON_TRIG Figure 13: Reference Circuit of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG95 supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 11: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET* 42 DI (U)SIM card hot-plug detection 1.8 V power domain.
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LPWA Module Series BG95 Hardware Design BG95 supports (U)SIM card hot-plug via the USIM_DET pin, and both high and low level detections are supported. The function is disabled by default, and please refer to AT+QSIMDET command in document [2] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.
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LPWA Module Series BG95 Hardware Design In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design:       Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide.
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LPWA Module Series BG95 Hardware Design USB_DM 10 GND 3 IO USB differential data (-) 90 Ω Ground For more details about USB 2.0 specification, please visit https://www.usb.org/. The USB interface is recommended to be reserved for firmware upgrade in application designs. The following figure shows a reference design of USB interface. Figure 16: Reference Design of USB Interface In order to ensure the integrity of USB data line signal, components R1 and R2 should be placed close to the module.
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LPWA Module Series BG95 Hardware Design 3.11. UART Interfaces The module provides three UART interfaces: the main UART, debug UART and the GNSS UART interfaces. Features of them are illustrated below:    The main UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400 bps, 460800 bps and 921600 bps baud rates, and the default is 115200 bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control.
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LPWA Module Series BG95 Hardware Design Table 14: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 22 DI Debug UART receive 1.8 V power domain DBG_TXD 23 DO Debug UART transmit 1.8 V power domain Table 15: Pin Definition of GNSS UART Interface Pin Name Pin No. I/O Description Comment GNSS_TXD 27 DO GNSS UART transmit BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain GNSS_RXD 28 DI GNSS UART receive 1.
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LPWA Module Series BG95 Hardware Design VDD_EXT VCCA 0.1uF 120K VCCB 0.1 μF VDD_MCU OE GND MAIN_RI A1 B1 RI_MCU MAIN_DCD A2 B2 DCD_MCU B3 CTS_MCU Translator MAIN_CTS A3 MAIN_RTS A4 B4 RTS_MCU MAIN_DTR A5 B5 DTR_MCU MAIN_TXD A6 B6 TXD_MCU MAIN_RXD A7 B7 A8 B8 51K RXD_MCU 51K Figure 17: Main UART Reference Design (Translator Chip) Please visit http://www.ti.com/ for more information. Another example with transistor translation circuit is shown as below.
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LPWA Module Series BG95 Hardware Design Figure 19: Reference Circuit with Dual-Transistor Circuit (Recommended for GNSS UART) NOTE GNSS_TXD is a BOOT_CONFIG pin (pin 27), therefore voltage-level translation IC solution with pull-up circuit or signal transistor/MOSFET circuit is not applicable to it. The dual-transistor circuit solution is recommended for GNSS UART. 3.12. PCM and I2C Interfaces* BG95 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface.
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LPWA Module Series BG95 Hardware Design Table 17: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK 4 DO PCM clock 1.8 V power domain. PCM_SYNC 5 DO PCM data frame sync 1.8 V power domain. PCM_DIN 6 DI PCM data input 1.8 V power domain. PCM_DOUT 7 DO PCM data output 1.8 V power domain. I2C_SCL 40 OD I2C serial clock (for external codec) Require external pull-up to 1.8 V.
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LPWA Module Series BG95 Hardware Design Table 18: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 21 DO Module network activity status indication 1.
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LPWA Module Series BG95 Hardware Design Table 20: Pin Definition of STATUS Pin Name STATUS Pin No. 20 I/O Description Comment DO Module operation status indication 1.8 V power domain The following figure shows a reference circuit of STATUS. Figure 22: Reference Design of STATUS 3.15. Behaviors of MAIN_RI AT+QCFG="risignaltype","physical" command can be used to configure MAIN_RI pin behavior. No matter on which port URC is presented, URC will trigger the behavior of MAIN_RI pin.
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LPWA Module Series BG95 Hardware Design 2. “*” means under development. 3.16. USB_BOOT Interface BG95 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the module to boot from USB port for firmware upgrade. Table 22: Pin Definition of USB_BOOT Interface Pin Name USB_BOOT Pin No. 75 I/O Description Comment DI Force the module into emergency download mode 1.8 V power domain. Active high. If unused, keep it open.
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LPWA Module Series BG95 Hardware Design Figure 24: Timing of Turning on Module with USB_BOOT NOTES 1. It is recommended to reserve the above circuit design during application design. 2. Please make sure that VBAT is stable before pulling down PWRKEY. It is recommended that the time between powering up VBAT and pulling down PWRKEY is no less than 30 ms. 3. When using MCU to control the module entering emergency download mode, please follow the above timing sequence.
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LPWA Module Series BG95 Hardware Design Table 23: Pin Definition of ADC Interface Pin Name Pin No. I/O Description Comment ADC0 24 AI General-purpose ADC interface ADC1 2 AI General-purpose ADC interface ADC0 and ADC1 cannot be used simultaneously. The following table describes the characteristics of ADC interfaces. Table 24: Characteristics of ADC Interfaces Parameter Min. Voltage Range 0.1 Typ. Max. Unit 1.8 V Resolution (LSB) 64.
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LPWA Module Series BG95 Hardware Design Table 25: Pin Definition of GPIO Interfaces Pin Name Pin No.
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LPWA Module Series BG95 Hardware Design Table 27: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 83 Generic RF controller 1.8 V power domain. Generic RF controller BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain. GRFC2 84 Table 28: Logic Levels of GRFC Interfaces Parameter Min. Max. Unit VOL 0 0.45 V VOH 1.35 1.
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LPWA Module Series BG95 Hardware Design 4 GNSS Receiver 4.1. General Description BG95 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, BG95 GNSS engine is switched off. It has to be switched on via AT command.
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LPWA Module Series BG95 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @open sky <3 m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
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LPWA Module Series BG95 Hardware Design 5 Antenna Interfaces BG95 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 31: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 IO Main antenna interface 50 Ω characteristic impedance 5.1.2.
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LPWA Module Series BG95 Hardware Design LTE-FDD B13 777–787 746–756 MHz LTE-FDD B18 815–830 860–875 MHz LTE-FDD B19 830–845 875–890 MHz LTE-FDD B20 832–862 791–821 MHz LTE-FDD B25 1850–1915 1930–1995 MHz LTE-FDD B26 1) 814–849 859–894 MHz LTE-FDD B27 1) 807–824 852–869 MHz LTE-FDD B28 703–748 758–803 MHz LTE-FDD B31 3) 452.5–457.5 462.5–467.
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LPWA Module Series BG95 Hardware Design Figure 25: Reference Design of Main Antenna Interface 5.1.4. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the clearance between RF traces and grounds (S).
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LPWA Module Series BG95 Hardware Design Figure 27: Coplanar Waveguide Design on a 2-layer PCB Figure 28: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 29: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) BG95_Hardware_Design 65 / 88
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LPWA Module Series BG95 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
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LPWA Module Series BG95 Hardware Design A reference design of GNSS antenna interface is shown as below. Figure 30: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna.
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LPWA Module Series BG95 Hardware Design Max Input Power: 50 W Input Impedance: 50 Ω Cable Insertion Loss: < 1 dB (LTE B5/B8/B12/B13/B18/B19/B20/B26/B27/B28/B71/B72/B73/B85, GSM850/EGSM900) Cable Insertion Loss: < 1.5 dB (LTE B1/B2/B3/B4/B25/B66, DCS1800/PCS1900) NOTE 1) It is recommended to use a passive GNSS antenna when LTE B13 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 5.3.2.
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LPWA Module Series BG95 Hardware Design U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 32: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 33: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com/.
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LPWA Module Series BG95 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 36: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.5 6.0 V VBAT_RF -0.3 6.0 V USB_VBUS -0.3 5.5 V Voltage at Digital Pins -0.3 2.09 V 6.2.
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LPWA Module Series BG95 Hardware Design IVBAT USB_VBUS Peak supply current (during transmission slot) Maximum power control level on EGSM900 USB detection BG95-M4 3.8 BG95-M3/ BG95-M5 1.8 BG95-M1/ BG95-M2/ BG95-M3/ BG95-N1/ BG95-M4/ BG95-M5 5.0 V 2.0 A V 6.3. Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 38: Operation and Storage Temperatures Parameter Min. Typ. Max.
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LPWA Module Series BG95 Hardware Design Table 39: BG95-M3 Current Consumption Description Conditions Average Max. Unit Leakage 1) Power-off @ USB and UART disconnected 14.5 - μA PSM 2) Power Saving Mode 3.9 - μA Rock Bottom AT+CFUN=0 @ Sleep mode 0.7 - mA LTE Cat M1 DRX = 1.28 s @ Paging = 24 ms 1.65 106 mA LTE Cat NB1 DRX = 1.28 s @ Paging = 24 ms 1.56 80 mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 20.48 s, DRX = 2.56 s 0.85 117 mA LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 20.
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LPWA Module Series BG95 Hardware Design LTE Cat NB1 data transfer (GNSS OFF) GPRS data transfer (GNSS OFF) EDGE data transfer (GNSS OFF) Band 28A @ 20.99 dBm 188 431 mA Band 28B @ 20.97 dBm 190 425 mA Band 66 @ 20.95 dBm 181 382 mA Band 85 @ 21.06 dBm 185 405 mA Band 1 @ 21.19 dBm 149 373 mA Band 2 @ 21.43 dBm 151 384 mA Band 3 @ 21.4 dBm 144 360 mA Band 4 @ 21.48 dBm 145 364 mA Band 5 @ 21.54 dBm 165 423 mA Band 8 @ 21.13 dBm 155 399 mA Band 12 @ 21.
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LPWA Module Series BG95 Hardware Design EDGE DCS1800 4UL/1DL @ 21 dBm 423 857 mA EDGE PCS1900 4UL/1DL @ 21 dBm 426 887 mA NOTES 1. 1) The current consumption in PSM is much lower than that in power off mode, and this is because of the following two designs:  More internal power supplies are powered off in PSM.  Also the internal clock frequency is reduced in PSM. 2) 2. The module’s USB and UART are disconnected and GSM network does not support PSM.
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LPWA Module Series BG95 Hardware Design GSM850/EGSM900 (8-PSK) 27 dBm ±3 dB 5 dBm ±5 dB DCS1800/PCS1900 (8-PSK) 26 dBm ±3 dB 0 dBm ±5 dB NOTES 1. 2. 3. 1) LTE-FDD B26 and B27 are supported by Cat M1 only. LTE-FDD B71 is supported by Cat NB2 only. 3) LTE-FDD B31, B72 and B73 are supported by BG95-M4 only. 2) 6.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG95.
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LPWA Module Series BG95 Hardware Design LTE-FDD B26 -108.2/-100.3 LTE-FDD B27 -108.4-100.8 LTE-FDD B28 -106.8/-100.8 LTE-FDD B66 -107.8/-101.8 LTE-FDD B71 Not Supported LTE-FDD B85 -108.4/-99.3 Table 43: Conducted RF Receiving Sensitivity of BG95-M2 Sensitivity ( dBm) Network LTE Band Primary Diversity Cat M1/3GPP Cat NB2 1)/3GPP LTE-FDD B1 -107/-102.3 -114/-107.5 LTE-FDD B2 -107/-100.3 -116/-107.5 LTE-FDD B3 -107/-99.3 -113/-107.5 LTE-FDD B4 -107/-102.3 -114/-107.
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LPWA Module Series BG95 Hardware Design LTE-FDD B27 -107/-100.8 Not Supported LTE-FDD B28 -107/-100.8 -115/-107.5 LTE-FDD B66 -107/-101.8 -115/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -107/-99.3 -115/-107.5 Table 44: Conducted RF Receiving Sensitivity of BG95-M3 Sensitivity ( dBm) Network LTE Band Primary Diversity Cat M1/3GPP Cat NB2 1)/3GPP LTE-FDD B1 -104.7/-102.3 -113/-107.5 LTE-FDD B2 -105/-100.3 -114/-107.5 LTE-FDD B3 -104.2/-99.3 -114/-107.
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LPWA Module Series BG95 Hardware Design LTE-FDD B66 -104.1/-101.8 -114/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -104.1/-99.3 -115/-107.5 Sensitivity ( dBm) Network Band Primary Diversity GSM/3GPP GSM850/EGSM900 GSM Supported DCS1800/PCS1900 -107/-102 Not Supported -107/-102 NOTES 1. 1) LTE Cat NB2 receiving sensitivity without repetitions. 2. “*” means under development. 6.7.
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LPWA Module Series BG95 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1. Top and Side Dimensions 19.9±0.15 2.2±0.2 23.6±0.
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LPWA Module Series BG95 Hardware Design 19.90±0.15 1.00 1.10 0.25 1.95 1.10 0.55 1.00 Pin 1 5.10 0.25 23.60±0.15 8.50 1.00 0.85 1.70 1.90 1.10 1.00 1.70 1.00 1.70 0.70 0.50 0.25 0.55 0.25 1.10 40x1.0 62x0.7 40x1.0 62x1.
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LPWA Module Series BG95 Hardware Design 7.2. Recommended Footprint 19.90±0.15 9.95 9.15 7.45 1.00 9.95 9.15 7.15 1.95 1.10 0.55 1.10 0.25 1.00 0.25 2.50 Pin 1 1.70 1.70 1.10 0.85 1.70 1.70 0.85 1.00 2.55 1.10 1.00 0.70 1.10 2.50 1.10 11.80 11.00 9.60 7.65 5.95 4.25 0.25 0.20 1.90 0.15 1.70 23.60±0.15 0.85 11.80 11.00 9.70 7.65 5.95 4.25 1.70 1.10 0.25 4.25 5.95 4.25 5.95 40x1.0 62x0.7 62x1.10 40x1.0 Figure 36: Recommended Footprint (Top View) NOTES 1. 2. 3.
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LPWA Module Series BG95 Hardware Design 7.3. Top and Bottom Views Figure 37: Top View of the Module Figure 38: Bottom View of the Module NOTE These are renderings of BG95 module. For authentic appearance, please refer to the module that you receive from Quectel.
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LPWA Module Series BG95 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG95 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in the vacuum-sealed bag: 12 months at < 40 ºC/90% RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤ 30 ºC/60% RH. Stored at < 10% RH. 3.
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LPWA Module Series BG95 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13–0.15 mm. For more details, please refer to document [5].
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LPWA Module Series BG95 Hardware Design Reflow Zone Max slope 2 to 3 °C/sec Reflow time (D: over 220 °C) 40 to 60 sec Max temperature 238 to 245 °C Cooling down slope 1 to 4 °C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging BG95 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The reel is 330 mm in diameter and each reel contains 250 modules.
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LPWA Module Series BG95 Hardware Design Figure 41: Reel Dimensions Table 47: Packaging Specifications of BG95 MOQ for MP Minimum Package: 250 Minimum Package × 4 = 1000 250 Size: 370 mm × 350 mm × 56 mm N.W: 0.61 kg G.W: 1.35 kg Size: 380 mm × 250 mm × 365 mm N.W: 2.45 kg G.W: 6.
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LPWA Module Series BG95 Hardware Design 9 Appendix A References Table 48: Related Documents SN Document Name Remark [1] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide [2] Quectel_BG95&BG77_AT_Commands_Manual BG95/BG77 AT Commands Manual [3] Quectel_BG95&BG77_GNSS_Application_Note BG95/BG77 GNSS Application Note [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 49: Terms and Abbrevi
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LPWA Module Series BG95 Hardware Design ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol D
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LPWA Module Series BG95 Hardware Design TX Transmitting Direction UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Abso
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LPWA Module Series BG95 Hardware Design 10 Appendix B GPRS Coding Schemes Table 50: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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LPWA Module Series BG95 Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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LPWA Module Series BG95 Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 BG95_Hardware_Design 92 / 88
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LPWA Module Series BG95 Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 52: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1 GMSK / 9.05 kbps 18.1 kbps 36.2 kbps CS-2 GMSK / 13.4 kbps 26.8 kbps 53.6 kbps CS-3 GMSK / 15.6 kbps 31.2 kbps 62.4 kbps CS-4 GMSK / 21.4 kbps 42.8 kbps 85.6 kbps MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps MCS-2 GMSK B 11.2 kbps 22.4 kbps 44.