RM500Q-AE&RM502Q-AE Hardware Design 5G Module Series Version: 1.0.0 Date: 2020-10-22 Status: Preliminary www.quectel.
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5G Module Series RM500Q-AE&RM502Q-AE Hardware Design About the Document Revision History Version Date Author Description - 2020-10-22 Jared WANG /Hank LIU Creation of the document 1.0.
G Module Series RM500Q-AE&RM502Q-AE Hardware Design Contents About the Document ................................................................................................................................. 45 Contents ..................................................................................................................................................... 56 Table Index ...........................................................................................................................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 4 GNSS Receiver ............................................................................................................................... 5272 4.1. General Description .............................................................................................................. 5272 4.2. GNSS Performance .............................................................................................................. 5272 5 Antenna Interfaces.......
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table Index Table 1: Frequency Bands and GNSS Type of RM500Q-AE&RM502Q-AE Module............................ 1412 Table 2: Key Features of RM500Q-AE&RM502Q-AE ........................................................................... 1513 Table 3: Definition of I/O Parameters..................................................................................................... 2219 Table 4: Pin Description .................................................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design RM500Q-AERM500Q-AE&RM502Q-AE Module .................. 错误!未定义书签。错误!未定义书签。10 错误!超链接引用无效。Table 2: Key Features of RM500Q-AERM500Q-AE&RM502Q-AE.. 错误!未定义书 签。错误!未定义书签。11 错误!超链接引用无效。Table 3: Definition of I/O Parameters ...... 错误!未定义书签。错误!未定义书签。17 错误!超链接引用无效。Table 4: Pin Description ..........................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 错误!超链接引用无效。Table 32: I/O Requirements .................... 错误!未定义书签。错误!未定义书签。62 错误!超链接引用无效。Table 33: Operation and Storage Temperatures 错误!未定义书签。错误!未定义书 签。62 错误!超链接引用无效。Table 34: RM500Q-AERM500Q-AE&RM502Q-AE Current Consumption.. 错误!未 定义书签。错误!未定义书签。63 错误!超链接引用无效。Table 35: RF Output Power..................... 错误!未定义书签。错误!未定义书签。68 错误!超链接引用无效。Table 36: RM500Q-AERM500Q-AE&RM502Q-AE Conducted RF Receiving Sensitivity ..........................................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment ........................................................................................................................... 21 Figure 3: Power Supply Limits during Radio Transmission .......................................................................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 42: Tray Size (Unit: mm) ................................................................................................................. 78 Figure 43: Tray Packaging Procedure .......................................................................................................
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 1 Introduction The hardware design defines RM500Q-AE&RM502Q-AE and describes the air and hardware interfaces which are connected with customers’ applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of RM500Q-AE&RM502Q-AE. To facilitate its application in different fields, reference design is also provided for reference.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 2 Product Concept 2.1. General Description RM500Q-AERM500Q-AE&RM502Q-AE isare a 5G NR/LTE-FDD/LTE-TDD/WCDMA wireless communication modules with receive diversity. It They provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks with standard PCI Express M.2 interface.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design ⚫ Other wireless terminal devices 2.2. Key Features The following table describes key features of RM500Q-AE&RM502Q-AE. Table 2: Key Features of RM500Q-AE&RM502Q-AE Feature Details Function Interface PCI Express M.2 Interface Power Supply ⚫ ⚫ Supply voltage: 3.135–4.4 V Typical supply voltage: 3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design ⚫ ⚫ ⚫ Downlink: QPSK, 16QAM and 64QAM and 256QAM Supports 1.4/3/5/10/15/20 MHz RF bandwidth Support downlink 4 × 4 MIMO on: B2/B4/B7/B25/B30/B38/B41/B48/B66 Max. transmission data rates 3): RM500QA-AE LTE: Max 1.0 Gbps(DL)/ 200 Mbps (UL) RM502QA-AE LTE: 2.0 Gbps (DL) /200 Mbps (UL) ⚫ ⚫ ⚫ Support 3GPP R8 DC-HSDPA, HSPA +, HSDPA, HSUPA and WCDMA Support QPSK, 16QAM and 64QAM modulation Max.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Temperature Range ⚫ ⚫ ⚫ ⚫ Operating temperature range: -20 to +60 °C 4) Restricted Operating temperature range: -30 to -20 °C, +60 to +75 °C Extended temperature range: -40 to -30 °C, +75 to +85 °C 5) Storage temperature range: -40 to +90°C Firmware Upgrade ⚫ USB 2.0 interface, PCIe interface and DFOTA RoHS ⚫ All hardware components are fully compliant with EU RoHS directive NOTES 1. 2. 3. 4. 5. 6. 1) HPUE is only for single carrier.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design VCC GND ET PMIC FULL_CARD_POWER_OFF# 38.4M XO SPMI Tx (U)SIM1 GPIOs Baseband Control WWAN_LED# WAKE_ON_WAN# DRx GNSS MIPI/G RFC W_DISABLE1# W_DISABLE2# Tx/Rx Blocks IQ PCIe × 1 RFFE ANT3_GNSSL1 PRx USB 2.0 & USB 3.1 Sub-6 GHz Transceiver PCI Express M.2 Key-B Interface RESET_N ANT2 ANT1 ANT0 NAND Flash 4Gb x8 LPDDR4X SDRAM 4Gb x16 Figure 1: Functional Diagram 2.3.2.4.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3 Application Interfaces The physical connections and signal levels of RM500Q-AE&RM502Q-AE comply with PCI Express M.2 specification.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of the module. The top side contains module and antenna connectors. No.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design No.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table 3: Definition of I/O Parameters Type Description AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output The following table shows the pin definition and description of the module. Table 4: Pin Description Pin No. Pin Name I/O Description 1 CONFIG_3 DO Not connected internally 2 VCC 3 GND 4 VCC 5 GND PI Power supply Comment Vmin = 3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 8 W_DISABLE1#* DI Airplane mode control. Active LOW. 9 USB_DM AI, AO USB 2.0 differential data (-) 10 WWAN_LED#* OD RF status indication LED 11 GND Ground 12 Notch Notch 13 Notch Notch 14 Notch Notch 15 Notch Notch 16 Notch Notch 17 Notch Notch 18 Notch Notch 19 Notch Notch 20 PCM_CLK* IO PCM data bit clock 21 CONFIG_0 DO Not connected internally 22 PCM_DIN* DI PCM data input 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 32 USIM_CLK DO (U)SIM clock 33 GND 34 USIM_DATA IO (U)SIM card data 35 USB_SS_RX_M AI USB 3.1 super-speed receive (-) 36 USIM_VDD PO (U)SIM card power supply 37 USB_SS_RX_P AI USB 3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design DO Used for external MIPI IC 1.8 V power domain control 56 RFFE_CLK* 57 GND 58 RFFE_DATA* DO Used for external MIPI IC 1.8 V power domain control 59 LAA_TX_EN DO Notification from SDR to WL when LTE transmitting 1.8 V power domain 60 WLAN_TX_EN DI Notification from WL to SDR while transmitting 1.8 V power domain 61 ANTCTL1* DO Antenna control 1.8 V power domain 62 COEX_RXD DI LTE/WLAN coexistence receive data 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design NOTE 1.Keep all NC, reserved and unused pins unconnected. 、 2.Pinpin 61/ and Ppin 63 isare used for ANTantenna tuner 3.3. Operating Modes The table below briefly summarizes the various operating modes to be mentioned in the following chapters. Table 5: Overview of Operating Modes Mode Details Normal Operation Idle Software is active. The module has registered on the network, and it is ready to send and receive data.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 2, 4, 70, 72, 74 VCC 3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73 GND PI 3.135–4.4 V 3.7 V typical DC supply Ground 3.3.1.3.4.1. Decrease Voltage Drop The power supply range of the module is from 3.135 V to 4.4 V. Please ensure that the input voltage will never drop below 3.135 V, otherwise the module will be powered off automatically. The following figure shows the maximum voltage drop during radio transmission in 3G/4G/5G networks.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Module VCC VCC D1 5.1 V + C1 100 μF C2 1 μF 2, 4, 70, 72, 74 C3 C4 C5 100 nF 33 pF 10 pF PMU 3, 5, 11, 27, GND 33, 39, 45, 51, 57, 71, 73 Figure 4: Reference Circuit of VCC Pins 3.3.2.3.4.2. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply is capable of providing a sufficient current of at least 3 A.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.4.3.5. Turn on and off Scenarios 3.4.1.3.5.1. Turn on the Module FULL_CARD_POWER_OFF# asynchronous signal is an Active Low input that is used to turn off the entire module. When the input signal is asserted high ( ≥ 1.19 V), the module will be enabled. When the input signal is driven low signal ( ≤ 0.2 V) or Tri-stated, it will force the module to shut down. This input signal is 3.3 V tolerant and can be driven by either 1.8 V or 3.3 V GPIO.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.4.1.1. Turn on the Module with a Host GPIO It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit is illustrated in the following figure. Host Module 1.8 V or 3.3 V GPIO FULL_CARD_POWER_OFF# 6 R4 100k PMU Note: The voltage of pin 6 should be no less than 1.19 V when it is at HIGH level. Figure 7: Turn on the Module with a Host GPIO NOTES 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design The timing of turning-off scenario is illustrated in the following figure. VCC RESET_N(H) FULL_CARD_POWER_OFF# ≥10 s Module Status RUNNING Power-off procedure OFF Figure 8: Turn-off Timing through FULL_CARD_POWER_OFF# 3.4.2.2.3.5.2.2. Turn off the Module through AT Command It is also a safe way to use AT+QPOWD command to turn off the module. For more details about the command, see document [2].
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design NOTE Please pull down FULL_CARD_POWER_OFF# pin immediately or cut off the power supply VCC when the host detects that the module USB/PCIe is removed. 3.6. Reset the Module RESET_N is an asynchronous and active low signal (1.8 5 V logic level). Whenever this pin is active, the module will immediately be placed in a Power On Reset (POR) condition.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Host Module VDD 1.5 V R1 100k RESET_N Reset pulse GPIO 67 Reset Logic Q2 NMOS R4 10R R5 100k 200-700 ms Figure 11: Reference Circuit of RESET_N with NMOS Driving Circuit Module VDD 1.5V R1 100k RESET_N 67 Reset Logic S1 TVS C1 33 pF 200-700 ms Note: The capacitor C1 is recommended to be less than 47 pF. The reset scenario is illustrated in the following figure. VCC ≤ 700 ms ≥200 ms RESET_N Module Status VIL ≤ 0.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.5.3.7. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C (1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 998: Pin Definition of (U)SIM Interfaces Pin No. Pin Name I/O Description Comment 36 USIM_VDD PO Power supply for (U)SIM card Class B (3.0 V) and Class C (1.8 V) 34 USIM_DATA IO (U)SIM card data 1.8/3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design USIM_VDD Module USIM_CLK 100 nF 10-20k USIM_VDD USIM_RST (U)SIM Card Connector VCC 22R RST 22R CLK USIM_DET CD 22R 33 pF GND 33 pF IO 33 pF USIM_DATA VPP GND TVS Note: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design USIM_VDD Module (U)SIM Card Connector 100 nF 10-20k USIM_VDD VCC 22R USIM_RST RST 22R USIM_CLK VPP CLK USIM_DET 22R 33 pF 33 pF GND IO 33 pF USIM_DATA GND TVS Note: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging, firmware upgrade and voice over USB*. Please note that only USB 2.0 can be used for firmware upgrade currently. The following table shows the pin definition of USB interface. Table 10109: Pin Definition of USB Interface Pin No.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Host Module USB_SS_TX_P USB_SS_TX_M C5 220 nF USB_SS_RX_P 37 C6 220 nF USB_SS_RX_M 35 USB_SS_TX_P 31 C1 220 nF USB_SS_TX_M 29 C2 220 nF USB_SS_RX_P USB_SS_RX_M USB_DM USB_DP R1 0Ω USB_DM 9 R2 0Ω USB_DP 7 BB R3 NM-0Ω Test Points R4 NM-0Ω ESD Minimize these stubs in PCB layout. Figure 16: Reference Circuit of USB 3.1 & 2.0 Interface AC coupling capacitors C5 and C6 must be placed close to the host and close to each other.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.7.3.9. PCIe Interface RM500Q-AE&RM502Q-AE modules provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Base Specification, Revision 3.0 and supports up to 8 Gbps per lane. ⚫ ⚫ PCI Express Base Specification Revision 3.0 compliant Data rate up to 8 Gbps per lane The following table shows the pin definition of PCIe interface. Table 111110: Pin Definition of PCIe Interface Pin No.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Host Module PCIE_REFCLK_P PCIE_REFCLK_M R4 0R PCIE_REFCLK_P 55 R5 0R PCIE_REFCLK_M 53 PCIE_TX_P C5 220 nF PCIE_RX_P 49 PCIE_TX_M C6 220 nF PCIE_RX_M 47 PCIE_TX_P 43 C1 220 nF PCIE_TX_M 41 C2 220 nF PCIE_RX_P PCIE_RX_M BB VCC_IO_HOST R1 100k R2 100k PCIE_WAKE_N PCIE_CLKREQ_N PCIE_RST_N R3 100k PCIE_WAKE_N 54 PCIE_CLKREQ_N 52 PCIE_RST_N 50 Note: The voltage level of VCC_IO_HOST depends on the host side due to the open dr
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 18: PCIe Power-on Timing Requirements of M.2 Specification Module power-on or insertion detection VCC tpower -on FUL L_CARD_ POWER_OFF System turn-on and booting RESET_N RFFE_ VIO _1V8 tturn-on VIH 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design ⚫ ⚫ Keep the differential impedance of PCIe data trace as 85 Ω ±10 %. You must not route PCIe data traces under components or cross them with other traces. 3.7.2.3.9.2. USB and PCIe Modes RM500Q-AE&RM502Q-AE supports to communicate through both USB and PCIe interfaces, respectively referring to the USB mode and the PCIe mode, as described below: USB Mode ⚫ ⚫ ⚫ Supports all USB 2.0/3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design reserved on bottom side) must be used for the firmware upgrade. Also, the firmware can be upgraded by the PCIe Card EVB, which could be inserted into a PC. For more details, see document [1]. 3.8.3.10. PCM Interface* RM500Q-AE&RM502Q-AE module supports audio communication via Pulse Code Modulation (PCM) digital interface.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 125 μs 1 PCM_CLK 2 31 32 PCM_SYNC MSB LSB MSB LSB PCM_DOUT PCM_DIN Figure 2122: Auxiliary Mode Timing The following table shows the pin definition of PCM interface which can be applied to audio codec design. Table 121211: Pin Definition of PCM Interface* Pin No. Pin Name I/O Description Comment 20 PCM_CLK IO PCM data bit clock 1.8 V power domain In master mode, it is an output signal. In slave mode, it is an input signal.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 3.9.3.11. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 131312: Pin Definition of Control and Indication Interfaces Pin No. Pin Name I/O Description Comment 8 W_DISABLE1#* DI Airplane mode control. Active LOW. 1.8/3.3 V 10 WWAN_LED#* OD Indicate RF status of the module. Open drain and active low signal. 23 WAKE_ON_WAN#* OD Wake up the host.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table 141413: RF Function Status W_DISABLE1# Level AT Commands RF Function Status High Level AT+CFUN=1 Enabled High Level AT+CFUN=0 AT+CFUN=4 Disabled Low Level AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 Disabled 3.9.2.3.11.2. W_DISABLE2#* RM500Q-AERM500Q-AE&RM502Q-AE module provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2# pin is pulled up by default. Driving it low will disable the GNSS function.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Host Module VCC_IO_HOST VDD 1.8 V R5 10k R6 10k GPIO GPIO R2 100k W_DISABLE2# 26 W_DISABLE1# 8 R3 100k BB Note: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically. Figure 22: W_DISABLE1# and W_DISABLE2# Reference Circuit 3.9.3. Figure 26: W_DISABLE1# and W_DISABLE2# Reference Circuit 3.9.4.3.11.3. WWAN_LED#* The WWAN_LED# signal is used to indicate RF status of the module, and its sink current is up to 10 mA.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table 161615: Network Status Indications of WWAN_LED# WWAN_LED# Level Description Low Level (LED ON) RF function is turned on High Level (LED OFF) RF function is turned off if any of the following occurs: ⚫ The (U)SIM card is not powered. ⚫ W_DISABLE1# is at low level (airplane mode enabled). ⚫ AT+CFUN=4 (RF function disabled). 3.9.5.3.11.4. WAKE_ON_WAN#* The WAKE_ON_WAN# is an open drain pin, which requires a pull-up resistor on the host.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design (Specific Absorption Rate) detection. The signal is sent from a host system proximity sensor to the module to provide an input trigger, which will reduce the output power in radio transmission. Table 181817: Function of the DPR Signal DPR Level Function High/Floating NO max. transmitting power backoff Low Max. transmitting power backoff by AT+QCFG="sarcfg" NOTE See document [2] for more details about AT+QCFG="sarcfg" command. 3.9.7.3.11.6.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design NOTE “*” means under development. 3.11.3.13. Antenna Tuner Control Interface* ANTCTL[1:2] are used for antenna tuner control and should be routed to an appropriate antenna control circuit. More details about the interface will be added in the future version of this document. Table 202019: Pin Definition of Antenna Tuner Control Interface Pin No.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 69 CONFIG_1 DO 0 Connected to GND internally 75 CONFIG_2 DO 0 Not connected internally 1 CONFIG_3 DO 0 Not connected internally The following figure shows a reference circuit of these four pins. Host Module VCC_IO_HOST R1 10k R2 10k R3 10k R4 10k GPIO GPIO GPIO GPIO NM-0Ω CONFIG_0 21 CONFIG_1 69 0Ω CONFIG_2 75 NM-0Ω CONFIG_3 1 NM-0Ω Note: The voltage level of VCC_IO_HOST depends on the host side and could be 1.8 V or 3.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 4 GNSS Receiver 4.1. General Description RM500Q-AE&RM502Q-AE module includes a fully integrated global navigation satellite system solution that supports Gen9-Lite of Qualcomm (GPS, GLONASS, BeiDou/Compass, and Galileo). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, the module GNSS engine is switched off. It has to be switched on via AT command.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Hot start @ open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @ open sky TBD m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after the loss of lock.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5 Antenna Interfaces RM500Q-AE&RM502Q-AE provides four antenna interfaces, the impedance of antenna port is 50 Ω. 5.1. RF Antenna Interfaces 5.1.1. Antenna Pin Definition The pin definition of RF antenna interfaces is shown below.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5.1.2.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design B26 814–849 859–894 B26 – – – WCS 2305–2315 2350–2360 B30 – – – B38 2570–2620 2570–2620 – B38 – n38 B41/B41-XGP 2496–2690 2496–2690 – B41 – n41 B48 3550–3700 3550–3700 – B48 – - B66 1710–1780 2110–2200 B66 – – n66 B71 663–698 617–652 B71 – – n71 n77 3300–4200 3300–4200 – – – n77 5.1.4. Reference Design of RF Antenna Interface A reference design of antenna interface is shown as below.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5.2. GNSS Antenna Interface The following table shows frequency specification of GNSS antenna connector. Table 272726: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42 ±1.023 (L1) MHz Galileo 1575.42 ±2.046 (E1) MHz QZSS 1575.42 (L1) MHz GLONASS 1597.5–1605.8 MHz BeiDou 1561.098 ±2.046 MHz NOTES 1. 2. 3. 4. 5. Keep the characteristic impedance for ANT3_GNSSL1 trace as 50 Ω.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Microstrip or coplanar waveguide is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip or coplanar waveguide with different PCB structures.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 3031: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design ANT0 ANT1 ANT2 ANT3_GNSS Figure 31: RM500Q-AE Antenna Connectors ANT0 ANT1 ANT2 ANT3_GNSS Figure 32: RM502Q-AE Antenna Connectors RM500Q-AE&RM502Q-AE_Hardware_Design 60 / 83
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5.4.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table 29: Antenna Requirements Type Requirements GNSS ⚫ ⚫ ⚫ ⚫ Frequency range: 1559–1606 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: >0 dBi ⚫ ⚫ ⚫ ⚫ VSWR: ≤ 3 Efficiency: > 30% Input Impedance: 50 Ω Cable insertion loss: < 1 dB WCDMA B5 LTE B5/B12/B13/B14/B17/B26/B71 5G NR n5/n12/n71 Cable insertion loss: < 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design The connector dimensions are illustrated as below: Figure 3334: RM500Q-AE&RM502Q-AE RF Connector Dimensions (Unit: mm) Table 303029: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Ω Temperature Rating -40 °C to +85 °C Voltage Standing Wave Ratio (VSWR) Meet the requirements of: Max 1.3 (DC–3 GHz) Max 1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 3435: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a Ø0.81 mm coaxial cable. Figure 3536: Connection between RF Connector and Mating Plug Using Ø0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a Ø1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 36: Connection between RF Connector and Mating Plug Using Ø1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 6 Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 31: Absolute Maximum Ratings Parameter Min. Max. Unit VCC -0.3 4.7 V Voltage at Digital Pins -0.3 2.3 V 6.2. Power Supply Requirements The typical input voltage of the module is 3.7 V, as specified by PCIe M.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 6.3. I/O Requirements Table 33: I/O Requirements Parameter Description Min. Max. Unit VIH Input high voltage 0.7 × VDD18 1) VDD18 +0.3 V VIL Input low voltage -0.3 0.3 × VDD18 V VOH Output high voltage VDD18-0.5 VDD18 V VOL Output low voltage 0 0.4 V NOTE 1) V DD18 is the I/O power domain of the module. 6.4. Operating and Storage Temperatures Table 34: Operationg and Storage Temperatures Parameter Min. Typ. Max.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. 6.5. Current Consumption Table 35: RM500Q-AE&RM502Q-AE Current Consumption Description Conditions Typ.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design LTE data transfer (GNSS OFF) 5G NR data transfer (GNSS OFF) WCDMA B4 HSDPA CH1638 @ 23 dBm TBD mA WCDMA B4 HSUPA CH1638 @ 23 dBm TBD mA WCDMA B5 HSDPA CH4407 @ 23 dBm TBD mA WCDMA B5 HSUPA CH4407 @ 23 dBm TBD mA LTE-FDD B2 CH900 @ 23 dBm TBD mA LTE-FDD B4 CH2175 @ 23 dBm TBD mA LTE-FDD B5 CH2525 @ 23 dBm TBD mA LTE-FDD B7 CH3100 @ 23 dBm TBD mA LTE-FDD B12 CH5095 @ 23 dBm TBD mA LTE-FDD B13 CH5230 @ 23 dBm TBD mA LTE-FDD B
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5G NR-FDD n2 CH387000 @ 23 dBm TBD mA 5G NR-FDD n2 CH392000 @ 23 dBm TBD mA 5G NR-FDD n2 CH397000 @ 23 dBm TBD mA 5G NR-FDD n5 CH174800 @ 23 dBm TBD mA 5G NR-FDD n5 CH176300 @ 23 dBm TBD mA 5G NR-FDD n5 CH177800 @ 23 dBm TBD mA 5G NR-FDD n7 CH525000 @ 23 dBm TBD mA 5G NR-FDD n7 CH531000 @ 23 dBm TBD mA 5G NR-FDD n7 CH537000 @ 23 dBm TBD mA 5G NR-FDD n12 CH146800 @ 23 dBm TBD mA 5G NR-FDD n12 CH147500 @ 23 dBm TBD mA 5G NR
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Table 363635: RF Output Power Mode Frequency Max. Min.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 5G NR LTE-FDD B13 (10 MHz) TBD TBD TBD -93.3 dBm LTE-FDD B14 (10 MHz) TBD TBD TBD -93.3 dBm LTE-FDD B17 (10 MHz) TBD TBD TBD -93.3 dBm LTE-FDD B25 (10 MHz) TBD TBD TBD -92.8 dBm LTE-FDD B26 (10 MHz) TBD TBD TBD -93.8 dBm LTE-FDD B30 (10 MHz) TBD TBD TBD -95.3 dBm LTE-TDD B38 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B41 (10 MHz) TBD TBD TBD -94.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 6.8. ESD Characteristics The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the module electrostatic discharge characteristics.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 37: Thermal Dissipation Area on Bottom Side of Module There are other measures to enhance heat dissipation performance: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Add ground vias as many as possible on PCB. Maximize airflow over/around the module. Place the module away from other heating sources. Module mounting holes must be used to attach (ground) the device to the main PCB ground.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design react with the PCB or shielding cover, and prevent the coating material from flowing into the module.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM500Q-AE&RM502Q-AE. All dimensions are measured in mm, and the tolerances are ±0.05 mm unless otherwise specified. 7.1.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 7.2.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. 7.3. M.2 Connector The module adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in document [5]. 7.4. Packaging The modules are packaged in trays. The following figure shows the tray size.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design Figure 4243: Tray Packaging Procedure RM500Q-AE&RM502Q-AE_Hardware_Design 79 / 83
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design 8 Appendix References Table 39: Related Documents SN. Document Name Remark [1] Quectel_PCIe_Card_EVB_User_Guide PCIe card EVB user guide [2] Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_ Manual AT commands manual for RG50xQ, RM5xxQ series [3] Quectel_RG50xQ&RM5xxQ_Series_GNSS_ Application_Note The GNSS application note for RG50xQ and RM5xxQ series [4] Quectel_RF_Layout_Application_Note RF layout application note [5] PCI Express M.
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design GSM Global System for Mobile Communications HSPA High Speed Packet Access HSUPA High Speed Uplink Packet Access kbps Kilo Bits Per Second LAA License Assisted Access LED Light Emitting Diode LTE Long Term Evolution Mbps Mega Bits Per Second ME Mobile Equipment MIMO Multiple-Input Multiple-Output MLCC Multiplayer Ceramic Chip Capacitor MO Mobile Originated MT Mobile Terminated PAP Password Authentication Protocol PCB Printed C
5G Module Series RM500Q-AE&RM502Q-AE Hardware Design UART Universal Asynchronous Receiver & Transmitter UL Uplink URC Unsolicited Result Code USB Universal Serial Bus (U)SIM (Universal) Subscriber Identity Module VIH Input High Voltage Level VIL Input Low Voltage Level VOH Output High Voltage Level VOL Output Low Voltage Level WCDMA Wideband Code Division Multiple Access Installation engineers need to be aware of the potential risk of the thermal effects of radio frequency energy and ho
FCC KDB996369 D03v01 Requirements List of applicable FCC rules FCC Part 15 Subpart B, Part 22 Subpart H, Part 24 Subpart E, Part 27 Subpart D & L & H & F & M & N, Part 90 Subpart R & S, Part 96 Summarize the specific operational use conditions Not Applicable Limited module procedures Not Applicable Trace antenna designs Refer to Manual Section 4 RF exposure considerations Refer to FCC certification requirements Antennas Technology Frequency Range Antenna Type Max Peak Gain (MHz) (dBi) WCDMA/LTE Band 2
Label and compliance information Refer to FCC Label Information on test modes and additional testing requirements Not Applicable Additional testing, Part 15 Subpart B disclaimer Refer to FCC 15B Report
FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
n66 3.53 n71 10.7 n77 6.11 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.
uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
