Product Info

ManualsBrandsQuectel ManualsElectronics5G Sub-6 GHz & mmWave M.2 Module

RM510Q-GL

Hardware Design

5G Module Series

Version: 1.0

Date: 2021-02-07

Status: Released

www.quectel.com

Summary of content (97 pages)

PAGE 1
RM510Q-GL Hardware Design 5G Module Series Version: 1.0 Date: 2021-02-07 Status: Released www.quectel.
PAGE 2
5G Module Series RM510Q-GL Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
PAGE 3
5G Module Series RM510Q-GL Hardware Design Copyright The information contained here is proprietary technical information of Quectel wireless solutions co., ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright © Quectel Wireless Solutions Co., Ltd. 2021.
PAGE 4
5G Module Series RM510Q-GL Hardware Design Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
PAGE 5
G Module Series RM510Q-GL Hardware Design About the Document Revision History Version Date Author Description - 2020-10-22 Kingson ZHANG /Jumping HE Creation of the document 1.
PAGE 6
5G Module Series RM510Q-GL Hardware Design Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ............................................................................................................................................
PAGE 7
5G Module Series RM510Q-GL Hardware Design 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 5 4.1.5. Without Hot-plug (U)SIM Card Connector ..................................................................... 39 4.1.6. (U)SIM Design Notices................................................................................................... 39 USB Interface ............................................................................................................................ 40 PCIe Interface .....................
PAGE 8
5G Module Series RM510Q-GL Hardware Design 5.4.4. Recommended RF Connector for Installation ............................................................... 69 5.4.4.1. Assemble Coaxial Cable Plug Manually ............................................................. 69 5.4.4.2. Assemble Coaxial Cable Plug with Jig ............................................................... 70 5.4.5. Recommended Manufacturers of RF Connector and Cable ......................................... 71 5.5.
PAGE 9
5G Module Series RM510Q-GL Hardware Design Table Index Table 1: Special Mark................................................................................................................................. 13 Table 1: Frequency Bands and GNSS Type of RM510Q-GL Module ....................................................... 14 Table 2: Key Features of RM510Q-GL ...................................................................................................... 15 Table 3: Definition of I/O Parameters......
PAGE 10
5G Module Series RM510Q-GL Hardware Design Table 41: Major Specifications of the RF Connector ................................................................................. 67 Table 42: Cellular Bands Supported by RM510Q-GL Antenna Connectors ............................................. 71 Table 43: Antenna Requirements .............................................................................................................. 71 Table 44: Power Supply Requirements ...................................
PAGE 11
5G Module Series RM510Q-GL Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment ........................................................................................................................... 19 Figure 3: DRX Run Time and Current Consumption in Sleep Mode .........................................................
PAGE 12
5G Module Series RM510Q-GL Hardware Design Figure 42: Tray Packaging Procedure .......................................................................................................
PAGE 13
5G Module Series RM510Q-GL Hardware Design 1 Introduction 1.1. Introduction The hardware design defines RM510Q-GL and describes the air and hardware interfaces which are connected with customers’ applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of RM510Q-GL. To facilitate its application in different fields, reference design is also provided for reference.
PAGE 14
5G Module Series RM510Q-GL Hardware Design 1.3. Special Mark Table 1: Special Mark Mark Definition * When an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin name, AT command, or argument is under development and currently not supported, unless otherwise specified. […] Brackets ([…]) used after a pin enclosing a range of numbers indicate all pin of the same type.
PAGE 15
5G Module Series RM510Q-GL Hardware Design 2 Product Concept 2.1. General Description RM510Q-GL is a 5G NR/LTE-FDD/LTE-TDD/WCDMA wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks. It is a standard M.2 Key-B WWAN module. For more details, see PCI Express M.2 Specification Revision 3.0, Version 1.2. RM510Q-GL is an industrial-grade module for industrial and commercial applications only.
PAGE 16
5G Module Series RM510Q-GL Hardware Design NOTES 1. 1) These bands work with mmWave antennas, and they support NSA only. 2. 2) These bands support receiving only. 3: This module supports mmWave Bands, and marketing without active mmWave antenna. We will provide software to host manufacturers when they use an active mmWave antenna with this module, this software will control the module work with active mmWave antenna. The host manufacturer can't use the active mmWave antenna directly.
PAGE 17
5G Module Series RM510Q-GL Hardware Design PCM Transmitting Power ⚫ ⚫ ⚫ ⚫ Used for audio function with external codec Support 16-bit linear data format Support long and short frame synchronization Support master and slave modes, but must be the master in long frame synchronization ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Class 3 (24 dBm +1/-3 dB) for WCDMA bands Class 3 (23 dBm ±2 dB) for LTE bands Class 3 (23 dBm ±2 dB) for 5G NR bands Class 2 (26 dBm ±2 dB) for LTE B38/B40/B41/B42/B43 bands HPUE 1) Class 2 (26 dBm +2/-3 dB) f
PAGE 18
5G Module Series RM510Q-GL Hardware Design HSUPA: Max 5.76 Mbps (UL) WCDMA: Max 384 kbps (DL)/384 kbps (UL) Rx-diversity ⚫ Supports 5G NR/LTE/WCDMA Rx-diversity GNSS Features ⚫ ⚫ Protocol: NMEA 0183 Data Update Rate: 1 Hz Antenna Interfaces ⚫ ANT0, ANT1, ANT2, and ANT3_GNSSL1 AT Commands ⚫ ⚫ Compliant with 3GPP TS 27.007 and 3GPP TS 27.
PAGE 19
5G Module Series RM510Q-GL Hardware Design 2.3. Evaluation Board To help you develop applications conveniently with the module, Quectel supplies an evaluation board (5G-mmWave-EVB), a USB micro-B cable, a USB type-C cable, antennas and other peripherals to control or test the module. For more details, see document [2] & document [3]. 2.4. Functional Diagram The following figure shows a block diagram of RM510Q-GL. ⚫ ⚫ ⚫ ⚫ ⚫ Power management Baseband LPDDR4X SDRAM + NAND Flash Radio frequency M.
PAGE 20
5G Module Series RM510Q-GL Hardware Design 2.5. Pin Assignment The following figure shows the pin assignment of the module. The top side contains module and antenna connectors. No.
PAGE 21
5G Module Series RM510Q-GL Hardware Design 2.6. Pin Description Table 4: Definition of I/O Parameters Type Description AI Analog Input AO Analog Output AIO Analog Input/Output DI Digital Input DO Digital Output DIO Digital Input/Output OD Open Drain PI Power Input PO Power Output PU Pull Up PD Pull Down The following table shows the pin definition and description of the module. Table 5: Pin Description Pin No.
PAGE 22
5G Module Series RM510Q-GL Hardware Design 5 GND Ground 6 FULL_CARD_ POWER_OFF# DI, PD Turn on/off the module. High level: Turn on Low level: Turn off 7 USB_DP AIO USB 2.0 differential data (+) 8 W_DISABLE1# DI, OD Airplane mode control. Active LOW. 9 USB_DM AIO USB 2.0 differential data (-) DO, OD RF status indication LED Active LOW. VIHmax = 4.4 V VIHmin = 1.19 V VILmax = 0.2 V 1.8/3.
PAGE 23
5G Module Series RM510Q-GL Hardware Design 27 GND 28 PCM_SYNC DI, PD PCM data frame sync 29 USB_SS_TX_M AO USB 3.1 super-speed transmit (-) 30 USIM1_RST DO, PD (U)SIM1 card reset 31 USB_SS_TX_P AO USB 3.1 super-speed transmit (+) 32 USIM1_CLK DO, PD (U)SIM1 clock 33 GND 34 USIM1_DATA DIO, PU (U)SIM1 card data 35 USB_SS_RX_M AI USB 3.1 super-speed receive (-) 36 USIM1_VDD PO (U)SIM1 card power supply 37 USB_SS_RX_P AI USB 3.
PAGE 24
5G Module Series RM510Q-GL Hardware Design 49 PCIE_RX_P AI PCIe receive (+) 50 PCIE_RST_N DI, OD PCIe reset. Active LOW 51 GND 52 PCIE_CLKREQ_N DO, OD PCIe clock request. Active LOW 53 PCIE_REFCLK_M AI, AO PCIe reference clock (-) 54 PCIE_WAKE_N DO, OD PCIe wake up Active LOW 55 PCIE_REFCLK_P AI, AO PCIe reference clock (+) 56 RFFE_CLK* 1) DO, PD Used for external MIPI IC control 57 GND 58 RFFE_DATA* 1) 59 LAA_TX_EN* Ground 1.
PAGE 25
5G Module Series RM510Q-GL Hardware Design internally 70 VCC 71 GND 72 VCC 73 GND PI Power supply Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V Ground PI Power supply Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V Ground 74 VCC PI Power supply 75 CONFIG_2 DO Not connected internally Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V NOTES 1. 1) If the function is required, please contact us for more details. 、 2. Keep all NC, reserved and unused pins unconnected.
PAGE 26
5G Module Series RM510Q-GL Hardware Design 3 Operating Characteristics 3.1. Operating Modes The table below briefly summarizes the various operating modes to be mentioned in the following chapters. Table 6: Overview of Operating Modes Mode Normal Operation Details Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data The module is connected to network.
PAGE 27
Current Consumption 5G Module Series RM510Q-GL Hardware Design DRX OFF ON OFF ON OFF ON OFF ON OFF Run Time Figure 3: DRX Run Time and Current Consumption in Sleep Mode The following section describes power saving procedure of module. If the host supports USB suspend/resume and remote wakeup function, the following two preconditions must be met to enable the module enter sleep mode. ⚫ ⚫ Execute AT+QSCLK=1 command to enable the sleep mode.
PAGE 28
5G Module Series RM510Q-GL Hardware Design 3.1.2. Airplane Mode The module provides a W_DISABLE1# pin to disable or enable airplane mode through hardware operation. See Chapter 4.5.1 for more details 3.2. Communication Interface with Host The module supports to communicate through both USB and PCIe interfaces, respectively referring to the USB mode and the PCIe mode as described below: USB Mode ⚫ ⚫ ⚫ Supports all USB 2.0/3.
PAGE 29
5G Module Series RM510Q-GL Hardware Design 3.3. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 7: Definition of VCC and GND Pins Pin Pin Name I/O Description DC Characteristics 2, 4, 70, 72, 74 VCC PI Power supply 3.135–4.4 V 3.7 V typical DC supply 3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73 GND Ground 3.3.1. Decrease Voltage Drop The input power supply range of the module is from 3.135 V to 4.4 V.
PAGE 30
5G Module Series RM510Q-GL Hardware Design Module VCC (3.7 V Typ.) VCC 2, 4 + C2 100 μF C4 1 μF C6 C8 C10 100 nF 33 pF 10 pF ET GND 3, 5, 11 VCC 70, 72, 74 D1 5.1 V + C1 100 μF C3 1 μF C5 C7 100 nF 33 pF C9 10 pF GND PMU 27, 33, 39, 45, 51, 57, 71, 73 Figure 6: Reference Circuit of VCC 3.3.2. Reference Design for Power Supply Power design for the module is important, as the performance of the module largely depends on the power source.
PAGE 31
5G Module Series RM510Q-GL Hardware Design NOTE To avoid damages to the internal flash, please cut off power supply after the module is turned off by pulling down FULL_CARD_POWER_OFF# pin for more than 7 s, and DON'T cut off power supply directly when the module is working. 3.3.3. Monitor the Power Supply AT+CBC command can be used to monitor the voltage value of VCC. For more details, see document [4] 3.4. Turn on 3.4.1. Turn on the Module FULL_CARD_POWER_OFF# (FCPO#) is used to turn on/off the module.
PAGE 32
5G Module Series RM510Q-GL Hardware Design Host Module 1.8 V or 3.3 V FULL_CARD_POWER_OFF# GPIO 6 R4 100k PMIC Note: The voltage of pin 6 should be no less than 1.19V when it is at HIGH level. Figure 8: Turn on the Module with a Host GPIO The timing of turn-on scenario is illustrated in the following figure. Module power-on or insertion detection 3.7 V VCC 1.5 V RESET# System turn-on and booting VIH ≥ 1.19 V FCPO# 68 ms 1.8 V RFFE_VIO_1V8 20 s 1.8 V or 3.
PAGE 33
5G Module Series RM510Q-GL Hardware Design 3.5. Turn off 3.5.1. Turn off the Module through FULL_CARD_POWER_OFF# For the design that turns on the module with a host GPIO, when the power is supplied to VCC, pulling down FULL_CARD_POWER_OFF# will turn off the module. The timing of turning-off scenario is illustrated in the following figure. 3.7 V VCC(H) 1.5 V RESET#(H) VIH ≥ 1.19 V FCPO# VIL ≤ 0.2 V 1.8 V RFFE_VIO_1V8 1.8 V or 3.
PAGE 34
5G Module Series RM510Q-GL Hardware Design 3.7 V VCC(H) 1.5 V RESET#(H) VIH ≥ 1.19 V FCPO# 1.8 V RFFE_VIO_1V8 1.8 V or 3.0 V USIM_VDD AT+QPOWD USB/PCIe removed USB/PCIe Module Status Running Turn-off procedure OFF Tturn-off Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# Table 11: Turn-off Time through AT Command and FULL_CARD_POWER_OFF# Symbol Min. Typ. Max. Comment Tturn-off 6.84 s - - System turn-off time NOTES 1.
PAGE 35
5G Module Series RM510Q-GL Hardware Design NOTE Triggering the RESET# signal will lead to loss of all data in the modem and removal of system drivers. It will also disconnect the modem from the network. The module can be reset by pulling down the RESET# pin for 250–600 ms. An open collector/drain driver or a button can be used to control the RESET# pin. Host Module VDD 1.
PAGE 36
5G Module Series RM510Q-GL Hardware Design The reset scenario is illustrated in the following figure. 3.7 V VCC(H) 1.5 V RESET# VIH ≥ 1.19 V FCPO#(H) TRST#-USIM 1.8 V RFFE_VIO_1V8 1.8 V or 3.0 V USIM_VDD Module Status Running Resetting Restarting 250 ms ≤ TRST# ≤ 600 ms Figure 14: Resetting Timing through RESET# Table 13: Resetting Time through RESET# Symbol Min. Typ. Max.
PAGE 37
5G Module Series RM510Q-GL Hardware Design 4 Application Interfaces The physical connections and signal levels of RM510Q-GL comply with PCI Express M.2 specification. This chapter mainly describes the definition and application of the following interfaces/pins of the module: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ (U)SIM interfaces USB interface PCIe interface PCM interface Control and indication interfaces Cellular/WLAN COEX interface* Antenna tuner control interface* Configuration pins 4.1.
PAGE 38
5G Module Series RM510Q-GL Hardware Design 4.1.2. Hot-plug of (U)SIM The module supports (U)SIM card hot-plug via the USIM_DET pin. (U)SIM card is detected by USIM_DET interrupt. (U)SIM card hot-plug is disabled by default. This is command enables (U)SIM card hot-plug function. The level of (U)SIM card detection pin should also be set when the (U)SIM card is inserted.
PAGE 39
5G Module Series RM510Q-GL Hardware Design 4.1.3. Normally Closed (U)SIM Card Connector With a normally closed (U)SIM card connector, the USIM_DET is normally short-circuited to ground when a (U)SIM card is not inserted, and the USIM_DET will change from low to high voltage level when a (U)SIM card is inserted. The rising edge indicates an insertion of the (U)SIM card. When the (U)SIM card is removed, USIM_DET will change from high to low voltage level.
PAGE 40
5G Module Series RM510Q-GL Hardware Design USIM_VDD Module (U)SIM Card Connector 100 nF 10k-20k USIM_VDD USIM_RST USIM_CLK VCC 22 Ω 1.8 V RST 22 Ω CLK USIM_DET USIM_DATA VPP 4.7k CD2 CD1 22 Ω IO GND 33k 33 pF 33 pF GND 33 pF TVS Note: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. Figure 16: Reference Circuit for Normally Open (U)SIM Card Connector 4.1.5.
PAGE 41
5G Module Series RM510Q-GL Hardware Design ⚫ ⚫ ⚫ ⚫ ⚫ Keep (U)SIM card signals away from RF and VCC traces. Make sure the ground between the module and the (U)SIM card connector is short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground.
PAGE 42
5G Module Series RM510Q-GL Hardware Design Host Module USB_SS_TX_P C5 220 nF USB_SS_RX_P 37 USB_SS_TX_M C6 220 nF USB_SS_RX_M 35 USB_SS_TX_P 31 C1 220 nF USB_SS_TX_M 29 C2 220 nF USB_SS_RX_P USB_SS_RX_M USB_DM USB_DP R2 0Ω USB_DM 9 R1 0Ω USB_DP 7 BB R3 NM-0Ω Test Points R4 NM-0Ω ESD Minimize these stubs in PCB layout. Figure 18: Reference Circuit of USB 3.1 & 2.0 Interface AC coupling capacitors C5 and C6 must be placed close to the host and close to each other.
PAGE 43
5G Module Series RM510Q-GL Hardware Design 4.3. PCIe Interface The module provides one integrated PCIe (Peripheral Component Interconnect Express) interface. ⚫ ⚫ PCI Express Base Specification Revision 3.0 compliant Data rate up to 8 Gbps per lane 4.3.1. PCIe Operating Mode The module supports endpoint (EP) mode and root complex (RC) mode. In EP mode, the module is configured as a PCIe EP device. In RC mode, the module is configured as a PCIe root complex.
PAGE 44
5G Module Series RM510Q-GL Hardware Design Table 16: Pin Definition of PCIe Interface Pin No. Pin Name I/O Description Comment 55 PCIE_REFCLK_P AIO PCIe reference clock (+) 53 PCIE_REFCLK_M AIO PCIe reference clock (-) 100 MHz. Require differential impedance of 85 Ω 49 PCIE_RX_P AI PCIe receive (+) 47 PCIE_RX_M AI PCIe receive (-) 43 PCIE_TX_P AO PCIe transmit (+) 41 PCIE_TX_M AO PCIe transmit (-) 50 PCIE_RST_N DI, OD PCIe reset. Active LOW.
PAGE 45
5G Module Series RM510Q-GL Hardware Design To ensure the signal integrity of PCIe interface, AC coupling capacitors C5 and C6 should be placed close to the host on PCB. C1 and C2 have been embedded into the module, so do not place these two capacitors on your schematic and PCB. The following principles of PCIe interface design should be complied with, so as to meet PCIe specification.
PAGE 46
5G Module Series RM510Q-GL Hardware Design Module power-on or insertion detection 3.7 V VCC 1.5 V RESET_N System turn-on and booting VIH ≥ 1.19 V FCPO# 1.8 V RFFE_VIO_1V8 TFCPO#-CLKREQ# > 90 ms PCIE_CLKREQ_N TFCPO#-PERST# > 100 ms TPERST#-CLK > 100 us PCIE_RST_N PCIE_REFCLK Tpower-on Tturn-on Figure 21: PCIe Power-up Timing of the Module Table 18: PCIe Power-up Timing of Module Symbol Min. Typ. Max. Comment Tpower-on 0m s 20 ms - System power-on time. It is depend on host device.
PAGE 47
5G Module Series RM510Q-GL Hardware Design The module supports audio communication via Pulse Code Modulation (PCM) digital interface. The PCM interface supports the following modes: ⚫ ⚫ Primary mode (short frame synchronization): the module works as both master and slave Auxiliary mode (long frame synchronization): the module works as master only In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB.
PAGE 48
5G Module Series RM510Q-GL Hardware Design The clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [4] for details about AT+QDAI command. 4.5. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 20: Pin Definition of Control and Indication Interfaces Pin No.
PAGE 49
5G Module Series RM510Q-GL Hardware Design Table 21: RF Function Status W_DISABLE1# Level AT Commands RF Function Status High Level AT+CFUN=1 Enabled (RF operation allowed) High Level AT+CFUN=0 AT+CFUN=4 Low Level AT+CFUN=1 Low Level AT+CFUN=0 AT+CFUN=4 Disabled (no RF operation allowed) 4.5.2. W_DISABLE2# The module provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2# pin is pulled up by default. Driving it low will disable the GNSS function.
PAGE 50
5G Module Series RM510Q-GL Hardware Design Host Module VCC_IO_HOST R5 10k VDD 1.8V R2 100k R6 10k GPIO GPIO W_DISABLE2# 26 W_DISABLE1# 8 R3 100k BB Notes: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically. Figure 24: W_DISABLE1# and W_DISABLE2# Reference Circuit 4.5.3. WWAN_LED# The WWAN_LED# signal is used to indicate RF status of the module, and its sink current is up to 10 mA.
PAGE 51
5G Module Series RM510Q-GL Hardware Design RF function is turned off if any of the following occurs: ⚫ The (U)SIM card is not powered. ⚫ W_DISABLE1# is at low level (airplane mode enabled). ⚫ AT+CFUN=4 (RF function disabled). High Level (LED OFF) 4.5.4. WAKE_ON_WAN# The WAKE_ON_WAN# is an open drain pin, which requires a pull-up resistor on the host. When a URC returns, a 1 s low level pulse signal will be outputted to wake up the host.
PAGE 52
5G Module Series RM510Q-GL Hardware Design Table 25: Function of the DPR Signal DPR Level Function High/Floating NO max. transmitting power backoff Low Max. transmitting power backoff by AT+QCFG="sarcfg" NOTE See document [4] for more details about AT+QCFG="sarcfg" command. 4.5.6. STATUS The module provides two status indication pins for communication with IPQ807x device.
PAGE 53
5G Module Series RM510Q-GL Hardware Design 4.7. Antenna Tuner Control Interface ANTCTL[1:2] and RFFE interface are used for antenna tuner control and should be routed to an appropriate antenna control circuit. More details about the interface will be added in the future version of this document. Table 27: Pin Definition of Antenna Tuner Control Interface Pin No. Pin Name I/O Description DC Characteristics 56 RFFE_CLK* 1) DO Used for external MIPI IC control 1.
PAGE 54
5G Module Series RM510Q-GL Hardware Design 69 CONFIG_1 DO Connected to GND internally - 75 CONFIG_2 DO Not connected internally - 1 CONFIG_3 DO Not connected internally - The following figure shows a reference circuit of these four pins. Host Module VCC_IO_HOST R1 10k R2 10k R3 10k R4 10k GPIO CONFIG_1 21 NM-0Ω 69 NM-0Ω GPIO CONFIG_2 75 0Ω CONFIG_3 1 NM-0Ω GPIO GPIO CONFIG_0 Notes: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically.
PAGE 55
5G Module Series RM510Q-GL Hardware Design 5 RF Characteristics This chapter mainly describes RF characteristics of the module. 5.1. mmWave IF Interfaces 5.1.1. Assignment and Definition of mmWave IF Interfaces The following figure and table show the assignment and definition of RM510Q-GL mmWave IF interfaces respectively.
PAGE 56
5G Module Series RM510Q-GL Hardware Design Table 30: Definition of mmWave IF Interfaces mmWave IF Interface I/O Functional Description IFH1 AIO Horizontal polarization IF output signal and control signal for mmWave RFIC device 1 IFH2 AIO Horizontal polarization IF output signal and control signal for mmWave RFIC device 2 IFH3 AIO Horizontal polarization IF output signal and control signal for mmWave RFIC device 3 IFH4 AIO Horizontal polarization IF output signal and control signal for mmWave
PAGE 57
5G Module Series RM510Q-GL Hardware Design 1.2–3.6 GHz < 4 dB 6–10 GHz < 7 dB (from the IFIC to the RFIC) < 5 dB (from the RM510-GL to QTM525) 5.1.2.3. IF Isolation IF isolation requirements for proper operation at 6–10 GHz operating frequency are as follows: Total system isolation between an IF path (combined PCB, cables, connectors, and so on) and the connected antenna module should be more than 35 dB, and the isolation between an IF path and other antenna modules should be more than 25 dB. 5.1.2.4.
PAGE 58
5G Module Series RM510Q-GL Hardware Design 2 3 4 IFH2 QTM527-2_IF1 (H) IF1 (H) IFV3 QTM527-2_IF2 (V) IF2 (V) IFV2 QTM527-3_IF2 (V) IF2 (V) IFH3 QTM527-3_IF1 (H) IF1 (H) IFV1 QTM527-4_IF2 (V) IF2 (V) IFH4 QTM527-4_IF1 (H) IF1 (H) QTM2_PON QTM3_PON QTM1_PON 5.1.4. IF Connector The dimensions of antenna receptacle (IPEX: 20981-001E-02) on the RM510Q-GL and plug (IPEX: 20980-001R-13) are illustrated as below.
PAGE 59
5G Module Series RM510Q-GL Hardware Design 5.2. Cellular Antenna Interfaces 5.2.1. Pin Definition The pin definition of antenna interfaces is shown below.
PAGE 60
5G Module Series RM510Q-GL Hardware Design 5G NR Antenna WCDMA 4G Refarmed ANT0 MHB_TRX MHB_TRX MHB_TRX UHB1) _PRX UHB 1) _PRX MIMO MIMO LB_TRX MHB_DRX ANT1 LB_TRX MIMO, UHB1)_DRX MIMO, LAA PRX ANT2 ANT3_ GNSSL1 LB_DRX MHB_DRX MIMO UHB (MHz) ） PRX n79 n78 (MHz) (MHz) 1452 3300 4400 to to to 2690 4200 5000 617 1452 3300 4400 to to to to 960 2690 4200 6000 617 1452 3300 4400 to to to to 960 2690 4200 5000 1452 3300 4400 to to to 2690 4200 600
PAGE 61
5G Module Series RM510Q-GL Hardware Design EGSM (950) 880–915 925–960 B8 – B8 n8 700 lower A–C 699–716 729–746 B12(B17) – – n12 700 upper C 777–787 746–756 B13 – – – 700 D 788–798 758–768 B14 – – – B18 815–830 860–875 B18 – – – B19 830–845 875–890 B19 – B19 – EU800 832–862 791–821 B20 – – n20 PCS + G 1850–1915 1930–1995 B25 – – n25 B26 814–849 859–894 B26 – – – 700 APAC 703–748 758–803 B28 – – n28 FLO – 717–728 B29 – – – WCS 2305
PAGE 62
5G Module Series RM510Q-GL Hardware Design 5.2.4. Sensitivity The following tables show conducted receiving sensitivity of RM510Q-GL. Table 38: RM510Q-GL Conducted Receiving Sensitivity Mode WCDMA LTE Frequency Primary Diversity SIMO 1) 3GPP (SIMO) WCDMA B1 -109.5 -110.3 -110.5 -106.7 dBm WCDMA B2 -109.5 -110.6 -110.5 -104.7 dBm WCDMA B3 -109.5 -110.4 -110.5 -103.7 dBm WCDMA B4 -109 -110.1 -110 -106.7 dBm WCDMA B5 -110.5 -112 -112 -104.7 dBm WCDMA B8 -109.5 -112 -111.
PAGE 63
5G Module Series RM510Q-GL Hardware Design 5G NR LTE-FDD B25 (10 MHz) -100.0 -101.5 -102.5 -92.8 dBm LTE-FDD B26 (10 MHz) -97.0 -99.3 -101.0 -93.8 dBm LTE-FDD B28 (10 MHz) -99.0 -101.3 -102.2 -94.8 dBm LTE-FDD B30 (10 MHz) -100.0 -101.5 -102.5 -95.3 dBm LTE-FDD B32 (10 MHz) TBD TBD TBD -95.3 dBm LTE-TDD B34 (10 MHz) -97.0 -98.5 -100.5 -96.3 dBm LTE-TDD B38 (10 MHz) -97.0 -98.3 -100.5 -96.3 dBm LTE-TDD B39 (10 MHz) -97.0 -97.0 -100.0 -96.
PAGE 64
5G Module Series RM510Q-GL Hardware Design (SCS: 15 kHz) 5G NR-FDD n28 (10 MHz) (SCS: 15 kHz) -95.0 -97.0 -99.0 -96.0 dBm 5G NR-TDD n38 (20 MHz) (SCS: 30 kHz) -94.0 -95.0 -97.0 -94.0 dBm 5G NR-TDD n40 (20 MHz) (SCS: 30 kHz) -93.5 -93.5 -95.5 -94.0 dBm 5G NR-TDD n41 (20 MHz) (SCS: 30 kHz) -85.0 -87.0 -88.5 -92.0 dBm 5G NR-FDD n48 (20 MHz) (SCS: 30 kHz) -94.0 -95.5 -97 -93.5 dBm 5G NR-FDD n66 (20 MHz) (SCS: 15 kHz) -91.5 -92.0 -94.5 -93.
PAGE 65
5G Module Series RM510Q-GL Hardware Design 5G NR 5G NR bands 23 dBm ±2 dB (Class 3) < -40 dBm (BW: 5–20 MHz) 1) 5G NR HPUE bands (n41/n77/n78/n79) 26 dBm +2/-3 dB (Class 2) < -40 dBm (BW: 5–20 MHz) 1) NOTE 1) For 5G NR TDD bands, the normative reference for this requirement is TS 38.101-1 [2] clause 6.3.1 5.3. GNSS Antenna Interface The following table shows frequency specification of GNSS antenna connector. 5.3.1.
PAGE 66
5G Module Series RM510Q-GL Hardware Design NOTES 1. 2. 3. 4. 5. Keep the characteristic impedance for the trace of GNSS antenna (ANT3_GNSSL1) to 50 Ω. Place the π-type matching components as close to the antenna as possible. Keep the digital circuits, such as that of (U)SIM card, USB interface, camera module, display connector and SD card, away from the antenna traces. Keep 75 dB isolation between each two antenna traces. Keep 15 dB isolation between each two antennas to improve the receiving sensitivity.
PAGE 67
5G Module Series RM510Q-GL Hardware Design 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after the loss of lock. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 5.4.
PAGE 68
5G Module Series RM510Q-GL Hardware Design Figure 31: RF Connector Dimensions (Unit: mm) Table 42: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Ω Temperature Rating -40 to +85 °C Voltage Standing Wave Ratio (VSWR) Meet the requirements of: Max 1.3 (DC–3 GHz) Max 1.4 (3–6 GHz) 5.4.3.
PAGE 69
5G Module Series RM510Q-GL Hardware Design Figure 32: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a Ø0.81 mm coaxial cable. Figure 33: Connection between RF Connector and Mating Plug Using Ø0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a Ø1.13 mm coaxial cable.
PAGE 70
5G Module Series RM510Q-GL Hardware Design Figure 34: Connection between RF Connector and Mating Plug Using Ø1.13 mm Coaxial Cable 5.4.4. Recommended RF Connector for Installation 5.4.4.1. Assemble Coaxial Cable Plug Manually The pictures for plugging in a coaxial cable plug is shown below, θ = 90°OK, θ ≠ 90°NG. Figure 35：Plug in A Coaxial Cable Plug The pictures of pulling out the coaxial cable plug is shown below, θ = 90°OK, θ ≠ 90°NG.
PAGE 71
5G Module Series RM510Q-GL Hardware Design Figure 36：Pull out Coaxial Cable Plug 5.4.4.2. Assemble Coaxial Cable Plug with Jig The pictures of installing the coaxial cable plug with a jig is shown below, θ = 90°OK, θ ≠ 90°NG.
PAGE 72
5G Module Series RM510Q-GL Hardware Design 5.4.5. Recommended Manufacturers of RF Connector and Cable For more details, visit https://www.i-pex.com. 5.5.
PAGE 73
5G Module Series RM510Q-GL Hardware Design WCDMA B1/B2/B3/B4 LTE B1/B2/B3/B4/B25/B32/B34/B39/B66 5G NR n1/n2/n3/n25/n66 Cable insertion loss: < 2 dB LTE B7/B30/B38/B40/B41/B42/B43/B46/B48 5G NR n7/n38/n40/n41/n48/n77/n78/n79 GNSS Frequency range: 1559–1606 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.
PAGE 74
5G Module Series RM510Q-GL Hardware Design 6 Electrical Characteristics and Reliability 6.1. Power Supply Requirements The typical input voltage of the module is 3.7 V, The following table shows the power supply requirements of the module. Table 45: Power Supply Requirements Parameter Description Min. Typ. Max. Unit VCC Power Supply 3.135 3.7 4.4 V Voltage Ripple – 30 100 mV Voltage Drop – – 165 mV 6.2.
PAGE 75
5G Module Series RM510Q-GL Hardware Design WCDMA @Paging Frame=64 31.06 mA WCDMA @Paging Frame=64, USB Active 52.42 mA LTE-FDD @DRX=0.64s 32.93 mA LTE-FDD @DRX=0.64s, USB Active 54.77 mA LTE-TDD @DRX=0.64s 32.85 mA LTE-TDD @DRX=0.64s, USB Active 54.
PAGE 76
5G Module Series RM510Q-GL Hardware Design 5G NR (GNSS OFF) LTE-FDD B5 CH2525 @ 23 dBm 485 mA LTE-FDD B7 CH3100 @ 23 dBm 745 mA LTE-FDD B8 CH3625 @ 23 dBm 495 mA LTE-FDD B12(B17) CH5095 @ 23 dBm 485 mA LTE-FDD B13 CH5230 @ 23 dBm 560 mA LTE-FDD B14 CH5330 @ 23 dBm 480 mA LTE-FDD B18 CH5925 @ 23 dBm 515 mA LTE-FDD B19 CH6075 @ 23 dBm 490 mA LTE-FDD B20 CH6300 @ 23 dBm 480 mA LTE-FDD B25 CH8365 @ 23 dBm 695 mA LTE-FDD B26 CH8865 @ 23 dBm 470 mA LTE-FDD B28 CH9435 @ 23 dBm 4
PAGE 77
5G Module Series RM510Q-GL Hardware Design 5G NR-TDD n77 CH620668 @ 26 dBm 500 mA 5G NR-TDD n77 CH650000 @ 26 dBm 500 mA 5G NR-TDD n77 CH679332 @ 26 dBm 520 mA 5G NR-TDD n78 CH620668 @ 26 dBm 500 mA 5G NR-TDD n78 CH636666 @ 26 dBm 530 mA 5G NR-TDD n78 CH652666 @ 26 dBm 500 mA 5G NR-TDD n79 CH695090 @ 26 dBm 550 mA 5G NR-TDD n79 CH713522 @ 26 dBm 550 mA 5G NR-TDD n79 CH731976 @ 26 dBm 530 mA 5G NR-FDD n1 CH423000 @ 23 dBm 950 mA 5G NR-FDD n1 CH428000 @ 23 dBm 880 mA 5G NR-FD
PAGE 78
5G Module Series RM510Q-GL Hardware Design 5G NR-FDD n8 CH191000 @ 23 dBm 520 mA 5G NR-FDD n12 CH146800 @ 23 dBm 480 mA 5G NR-FDD n12 CH147500 @ 23 dBm 480 mA 5G NR-FDD n12 CH148200 @ 23 dBm 480 mA 5G NR-FDD n20 CH159200 @ 23 dBm 480 mA 5G NR-FDD n20 CH161200 @ 23 dBm 480 mA 5G NR-FDD n20 CH163200 @ 23 dBm 490 mA 5G NR-FDD n25 CH387000 @ 23 dBm 640 mA 5G NR-FDD n25 CH392500 @ 23 dBm 750 mA 5G NR-FDD n25 CH398000 @ 23 dBm 680 mA 5G NR-FDD n28 CH152600 @ 23 dBm 550 mA 5G NR-F
PAGE 79
5G Module Series RM510Q-GL Hardware Design WCDMA voice call* 5G NR-FDD n71 CH126900 @ 23 dBm 480 mA 5G NR-FDD n71 CH129400 @ 23 dBm 490 mA WCDMA B1 CH10700 @ 23 dBm 670 mA WCDMA B2 CH9800 @ 23 dBm 730 mA WCDMA B3 CH1338 @ 23 dBm 650 mA WCDMA B4 CH1638 @ 23 dBm 600 mA WCDMA B5 CH4408 @ 23 dBm 460 mA WCDMA B6 CH4175 @ 23 dBm 460 mA WCDMA B8 CH3012 @ 23 dBm 475 mA WCDMA B19 CH338 @ 23 dBm 460 mA 6.3. Digital I/O Characteristic Table 47: Logic Levels of Digital I/O (1.
PAGE 80
5G Module Series RM510Q-GL Hardware Design VIL Input low voltage -0.3 0.2 × USIM_VDD V VOH Output high voltage 0.8 × USIM_VDD USIM_VDD V VOL Output low voltage 0 0.4 V Table 49: (U)SIM 3.0 V I/O Requirements Parameter Description Min. Max. Unit USIM_VDD Power supply 2.7 3.05 V VIH Input high voltage 0.7 × USIM_VDD USIM_VDD + 0.3 V VIL Input low voltage -0.3 0.2 × USIM_VDD V VOH Output high voltage 0.8 × USIM_VDD USIM_VDD V VOL Output low voltage 0 0.4 V 6.4.
PAGE 81
5G Module Series RM510Q-GL Hardware Design performance while working under extended temperatures or extreme conditions (such as with maximum power or data rate) for a long time, it is strongly recommended to add a thermal pad or other thermally conductive compounds between the module and the main PCB for thermal dissipation. The thermal dissipation area on the bottom (i.e.
PAGE 82
5G Module Series RM510Q-GL Hardware Design heatsink and the module, and the heatsink should be designed with as many fins as possible to increase heat dissipation area. NOTE If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 6.6.
PAGE 83
5G Module Series RM510Q-GL Hardware Design the module meets 3GPP specifications. 2. 2) To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction.
PAGE 84
5G Module Series RM510Q-GL Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM510Q-GL. All dimensions are measured in mm, and the tolerances are ±0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 39: Mechanical Dimensions of the Module (Unit: mm) NOTE Images above are for illustration purpose only and may differ from the actual module.
PAGE 85
5G Module Series RM510Q-GL Hardware Design 7.2. Top and Bottom Views of the Module TOP VIEW BOT VIEW Figure 40: RM510Q-GL Top View and Bottom View 7.3. M.2 Connector The module adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in PCI Express M.2 Specification Rev3.0. 7.4. Packaging The modules are packaged in trays. The following figure shows the tray size.
PAGE 86
5G Module Series RM510Q-GL Hardware Design Figure 41: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below. 1. 2. 3. 4. 5. 6. Use 10 trays to package 100 modules at a time (tray size: 247 mm × 172 mm). Place an empty tray on the top of the 10-tray stack. Fix the stack with masking tape in “#” shape as shown in the following figure. Pack the stack with conductive bag, and then fix the bag with masking tape.
PAGE 87
5G Module Series RM510Q-GL Hardware Design 8 Appendix References Table 53: Related Documents SN.
PAGE 88
5G Module Series RM510Q-GL Hardware Design ET Envelope tracking FDD Frequency Division Duplexing FR2 Frequency Range 2 GLONASS Global Navigation Satellite System (Russia) GNSS Global Navigation Satellite System GPS Global Positioning System GSM Global System for Mobile Communications HSPA High Speed Packet Access HSUPA High Speed Uplink Packet Access IF Intermediate Frequency kbps Kilo Bits Per Second LAA License Assisted Access LED Light Emitting Diode LO Local Oscillator LTE
PAGE 89
5G Module Series RM510Q-GL Hardware Design PCB Printed Circuit Board PCIe Peripheral Component Interconnect Express PCM Pulse Code Modulation PDU Protocol Data Unit PPP Point-to-Point Protocol RF Radio Frequency RFFE RF Front-End RFIC Radio-frequency Integrated Circuit Rx Receive SAR Specific Absorption Rate SCS Sub-carrier Spacing SMS Short Message Service TCP Transmission Control Protocol Tx Transmit UART Universal Asynchronous Receiver & Transmitter UDP User Datagram Proto
PAGE 90
5G Module Series RM510Q-GL Hardware Design WCDMA Wideband Code Division Multiple Access RM510Q-GL_Hardware_Design 89 / 88
PAGE 91
OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
PAGE 92
Antenna (1) The antenna must be installed such that 20 cm is maintained between the antenna and users, (2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product.
PAGE 93
Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
PAGE 94
This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
PAGE 95
Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
PAGE 96
Cet appareil est conçu uniquement pour les intégrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit être installée de telle sorte qu'une distance de 20 cm est respectée entre l'antenne et les utilisateurs, et 2) Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplémentaires sur l'émetteur ne seront pas nécessaires.
PAGE 97
Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.