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AG521R-NA QuecOpen

Hardware Design

Automotive Module Series

Version: 1.0.0

Date: 2021-01-26

Status: Preliminary www.quectel.com

Summary of content (99 pages)

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AG521R-NA QuecOpen Hardware Design Automotive Module Series Version: 1.0.0 Date: 2021-01-26 Status: Preliminary www.quectel.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design The information contained here is proprietary technical information of Quectel Wireless Solutions Co., Ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright © Quectel Wireless Solutions Co., Ltd. 2020.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design About the Document Revision History Version Date Author Description - 2020-04-04 Leon HUANG/ Alex ZHANG/ Evan SHEN/ Creation of the document 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Contents About the Document ................................................................................................................................................... 3 Contents ....................................................................................................................................................................... 4 Table Index...................................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.13. 3.14. 3.15. 3.16. 3.17. 3.18. 3.19. SDIO Interface ........................................................................................................................................ 53 SPI Interfaces .......................................................................................................................................... 56 RGMII Interface ................................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table Index Table 1: Frequency Bands of AG521R-NA QuecOpen® Module .............................................................................. 12 Table 2: Key Features ................................................................................................................................................ 13 Table 3: I/O Parameters Definition .................................................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 42: GPRS Multi-slot Classes ........................................................................................................................... 91 Table 43: EDGE Modulation and Coding Schemes ..................................................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure Index Figure 1: Functional Diagram for AG521R-NA QuecOpen® .................................................................................... 16 Figure 2: Pin Assignment (Top View) ....................................................................................................................... 18 Figure 3: Sleep Mode Current Consumption Diagram .........................................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 42: Top View of the Module ........................................................................................................................... 83 Figure 43: Bottom View of the Module ..................................................................................................................... 83 Figure 44: Recommended Reflow Soldering Thermal Profile ............................................................................
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 1 Introduction QuecOpen® is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the advantages of QuecOpen® solution. Especially, its advantage in reducing the product cost is greatly valued by customers.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 2 Product Concept 2.1. General Description AG521R-NA QuecOpen module is a baseband processor platform based on ARM Cortex A7 kernel. The maximum dominant frequency is up to 1.497 GHz. AG521R-NA QuecOpen module is a series of automotive-grade LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication modules with receive diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA, EDGE and GPRS networks.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design NOTE 1. 1) LTE-FDD B29, B30 and B32 support Rx only. 2.2. Key Features The following table describes detailed features of the module. Table 2: Key Features Feature Details Power Supply VBAT_BB/VBAT_RF: ⚫ Supply voltage: 3.3–4.3 V ⚫ Typical supply voltage: 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ ⚫ LTE: AMR/AMR-WB Support echo cancellation and noise suppression I2S Interface Used for external codec function PCM Interface ⚫ ⚫ ⚫ ⚫ Used for external BT function Support 16-bit linear data format Support long frame sync and short frame sync Support master and slave modes, but must be the master in long frame sync ⚫ USB Interfaces UART Interfaces USB 3.0 and 2.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ Storage temperature range: -40 °C to +95 °C Firmware Upgrade ⚫ ⚫ USB 2.0 interface DFOTA RoHS All hardware components are fully compliant with EU RoHS directive NOTES 1. 2. 3. 4. 1) Within operation temperature range, the module is 3GPP compliant, and emergency call can be dialed out with a maximum power and data rate.
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ANT_MAIN ANT_DIV ANT_GNSS Automotive Module Series AG521R-NA QuecOpen Hardware Design Diplexer Diplexer 2G PA+DP16T Diplexer DP12T VBAT_RF ... ... L1 SAW L2&L5 SAW DRx SAWs ... QLNA*2 ... Duplexers, SAWs and Qualplexers APT or ET ... ... QLNA*2 MMPA ... NAND LPDDR4 Transceiver VBAT_BB VREG_UIM1 QLINK Control VREG_UIM2 VDD_EXT PMIC Control Baseband PWRKEY RESET_N ADCx2 LED 38.4M XO NET_STATUS Audio SPKs MICs PCM I2S PCIe USB2.0&3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3 Application Interfaces 3.1. General Description The module is designed with 400 LGA pins that can be connected to cellular application platforms. Module interfaces are described in detail in the following sub-chapters: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Power supply (U)SIM interfaces USB 2.0/3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design GND 399 GND GND 140 137 GND 138 143 ANT_MAIN GND 141 146 GND GND 144 GND GND 147 149 RESERVED GND 150 GND 155 152 GND 153 158 GND GND 156 161 RESERVED GND 159 GND GND 162 GND 164 GND 165 ANT_DIV 170 167 GND 168 173 GND GND 171 GND 176 174 GND RESERVED GND 177 GND 182 179 GND 180 GND 185 183 GND RESERVED GND 186 GND 188 GND 189 GND 194 191 GND 192 197 RESERVED GND 195 199
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Automotive Module Series AG521R-NA QuecOpen Hardware Design NOTES 1. 2. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition of the module and the alternate functions of multiplexing pins.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 4: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 241, 242, 244 PI Power supply for the module’s baseband part Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V It must be provided with sufficient current up to 0.8 A. VBAT_RF 109, 111, 112, 114 235, 236 238, 239 PI Power supply for the module’s RF part Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design USIM1_VDD 251 PO (U)SIM1 card power supply IOmax = 50 mA For 1.8 V (U)SIM: Vmax = 1.9 V Vmin = 1.7 V For 3.0 V (U)SIM: Vmax = 3.05 V Vmin = 2.7 V For 1.8 V (U)SIM: VILmax = 0.36 V VIHmin = 1.26 V VOLmax = 0.4 V VOHmin = 1.44 V USIM1_DATA 254 IO (U)SIM1 card data For 3.0 V (U)SIM: VILmax = 0.57 V VIHmin = 2.0 V VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V USIM1_CLK 253 DO (U)SIM1 card clock For 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design IOmax = 50 mA For 1.8 V (U)SIM: VILmax = 0.36 V VIHmin = 1.26 V VOLmax = 0.4 V VOHmin = 1.44 V USIM2_DATA 257 IO (U)SIM2 card data For 3.0 V (U)SIM: VILmax = 0.57 V VIHmin = 2.0 V VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V USIM2_CLK 259 DO (U)SIM2 card clock For 3.0 V (U)SIM: VOLmax = 0.4 V VOHmin = 2.28 V For 1.8 V (U)SIM: VOLmax = 0.4 V VOHmin = 1.44 V USIM2_RST 260 DO (U)SIM2 card reset For 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design USB_SS_TX_P 93 AO USB 3.0 super-speed transmit (+) USB_SS_TX_M 91 AO USB 3.0 super-speed transmit (-) USB_SS_RX_P 90 AI USB 3.0 super-speed receive (+) USB_SS_RX_M 88 AI USB 3.0 super-speed receive (-) Pin Name Pin No.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design UART1_TXD 70 DO UART1 transmit VOLmax = 0.45 V VOHmin = 1.35 V 72 DI UART1 receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V Pin Name Pin No. I/O Description DC Characteristics BT_UART_TXD 59 DO BT UART transmit VOLmax = 0.45 V VOHmin = 1.35 V BT UART receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design I2S Interface (for Codec Configuration by Default) Pin Name Pin No. I/O Description DC Characteristics CDC_RST 77 DO Codec reset VOLmax = 0.45 V VOHmin = 1.35 V I2S_MCLK 81 DO Clock output for codec VOLmax = 0.45 V VOHmin = 1.35 V I2S_WS 265 IO I2S word select VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V I2S_SCK 262 DO I2S clock VOLmax = 0.45 V VOHmin = 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design PCIe Interface Pin Name I/O Description PCIE_REFCLK_ 40 P AO PCIe reference clock (+) PCIE_REFCLK_ 38 M AO PCIe reference clock (-) PCIE_TX_M 44 AO PCIe transmit (-) PCIE_TX_P 46 AO PCIe transmit (+) PCIE_RX_M 32 AI PCIe receive (-) PCIE_RX_P 34 AI PCIe receive (+) PCIE_CLKREQ PCIE_RST Pin No. 36 39 IO DO PCIe clock request DC Characteristics Comment Require differential impedance of 95 Ω.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII_RX_3 17 DI RGMII receive data bit 3 RGMII_CK_RX 19 DI RGMII receive clock RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bit 3 DO Enable external LDO to supply power to RGMII_PWR_IN PI Power input for internal R
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Automotive Module Series AG521R-NA QuecOpen Hardware Design SDC1_CMD 48 IO SDIO command SDC1_DATA_4 53 IO SDIO data bit 4 SDC1_DATA_5 55 IO SDIO data bit 5 SDC1_DATA_6 56 IO SDIO data bit 6 SDC1_DATA_7 58 IO SDIO data bit 7 SDC1_CLK 47 DO VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain Can be configured to GPIOs. If unused, keep them open. SDIO clock VOLmax = 0.45 V VOHmin = 1.4 V 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Pin Name Pin No. I/O Description DC Characteristics USB_BOOT 83 DI Force the module into emergency download mode BT_EN 66 DO BT function enable control VOLmax = 0.45 V VOHmin = 1.35 V DR_SYNC 95 DO Navigation 1PPS time sync output VOLmax = 0.45 V VOHmin = 1.35 V IMU interrupt 1 VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V IMU_INT1 169 DI IMU_INT2 187 DI IMU interrupt 2 VILmin = -0.3 V VILmax = 0.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Pin Name Pin No. I/O Description ANT_MAIN 143 AI/ AO Main antenna interface AI Diversity antenna interface ANT_DIV 170 DC Characteristics Comment 50 Ω impedance. RESERVED Pins Pin Name RESERVED Pin No.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 5: Alternate Functions of Multiplexing Pins Pin No. Pin Name 27 RGMII_PWR_EN 29 RGMII_INT 31 Default Function Reset 1) Wake up Interrupt 2) Power Domain BS-PD, L Y 1.8 V BS-PD, L Y 1.8 V RGMII_RST BS-PD, L Y 1.8 V 30 PCIE_WAKE BS-PD, L Y 1.8 V 36 PCIE_CLKREQ BS-PD, L Y 1.8 V 39 PCIE_RST BS-PD, L Y 1.8 V 45 EMMC_PWR_EN BS-PD, L Y 1.8 V 53 SDC1_DATA_4 BSH-PD, L N 1.8 V 54 EMMC_RST BS-PD, L Y 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 71 UART1_CTS GPIO_23 BS-PD, L N 1.8 V 72 UART1_RXD GPIO_21 BS-PU, L Y 1.8 V 74 UART1_RTS GPIO_22 BS-PD, L Y 1.8 V 107 DBG_TXD BS-PD, L N 1.8 V 110 DBG_RXD BS-PD, L Y 1.8 V 73 PCM_SYNC 75 PCM_CLK I2S_WS GPIO_12 BS-PD, L Y 1.8 V I2S_SCK GPIO_15 BS-PD, L Y 1.8 V PCM 76 PCM_IN I2S_DIN GPIO_13 BS-PD, L Y 1.8 V 78 PCM_OUT I2S_DOUT GPIO_14 BS-PD, L Y 1.8 V 77 CDC_RST GPIO_86 BS-PD, L Y 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 259 USIM2_CLK BSH-PD, L N 1.8/2.85 V 257 USIM2_DATA BSH-PD, L N 1.8/2.85 V 258 USIM2_DET BS-PD, L Y 1.8 V 210 SPI1_MOSI GPIO_72 BS-PD, L N 1.8 V 213 SPI1_CS GPIO_74 BS-PD, L N 1.8 V SPI 216 SPI1_CLK GPIO_75 BS-PD, L Y 1.8 V 219 SPI1_MISO GPIO_73 BS-PD, L N 1.8 V 66 BT_EN BS-PD, L Y 1.8 V 83 USB_BOOT BS-PD, L N 1.8 V 95 DR_SYNC BS-PD, L Y 1.8 V 169 IMU_INT1 GPIO_88 BS-PD, L Y 1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 246 GPIO7 BS-PD, L Y 1.8 V 249 GPIO8 L N 1.8 V NOTES 1. “Alternate Function 1/2” takes effect only after software configuration. 2. 1) See Table 4 for more details about the symbol description. 3. 2) If the GPIOs without interrupt function are configured as interrupt GPIOs, power consumption of the module will be increased. (“Y” means “interrupt function supported”. “N” means “interrupt function not supported”.) 4.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 6: Overview of Operating Modes Mode Details Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 3: Sleep Mode Current Consumption Diagram NOTE DRX cycle index values are broadcasted by the base station through the wireless network. 3.5.1.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter sleep mode. ⚫ ⚫ ⚫ Use sleep API to enable the sleep mode.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ ⚫ ⚫ Use sleep & wakeup API to enable the sleep mode. Ensure the level of pins that configured as wake-up interrupt in Table 5 are under non-wakeup status. The host’s USB bus, which is connected with the module’s USB interface, enters suspended state. The following figure shows the connection between the module and the host.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 6: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. 3.5.2. Airplane Mode When the module enters airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. The mode can be set via AT+CFUN= command.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3 to 4.3 V. Please make sure that the input voltage will never drop below 3.3 V. The following figure shows the voltage drop during burst transmission in 2G network. The voltage drop will be less in 3G and 4G networks. Burst Transmission Burst Transmission VBAT Ripple Drop Min.3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. If the voltage drop between the input and output is not too high, it is recommended to use an LDO to supply power for the module. If there is a big voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as the power supply.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design PWRKEY 7 VIHmax = 1.89 V VIHmin = 1.17 V VILmax = 0.63 V Turn on/off the module 1.8 V power domain. Pulled-up internally. Active low. When the module is in power-off mode, it can be turned on by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. PWRKEY 500 ms 4.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Note 1 ≥ 500 ms VBAT VIH ≥ 1.17 V PWRKEY VIL ≤ 0.63 V RESET TBD UART I nactive Active TBD USB I nactive Active TBD VDD_ EXT Figure 12: Power-on Timing NOTES 1. Please make sure that VBAT is stable for at least 30 ms before pulling down PWRKEY pin. 2. It is recommended to use an external OD/OC circuit to control the PWRKEY pin. 3.7.2. Turn on Module with PON_1 Table 9: PON_1 Pin Description Pin Name Pin No.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design PON_1 10K 0.78– 1.89 V PVIN SS/TR Module Figure 13: Turn on the Module using PON_1 NOTE If PON_1 is not used, it is recommended to connect it to the ground. 3.7.3. Turn off Module Either of the following methods can be used to turn off the module: ⚫ ⚫ Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using API interface. 3.7.3.1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.7.3.2. Turn off Module Using API Interface It is also a safe way to use API interface to turn off the module, which is similar to turning off the module via PWRKEY Pin. See document [2] for details about API function. NOTES 1. 2. To avoid damaging the internal flash, please do not switch off the power supply when the module works normally. Only after the module is shut down by PWRKEY or API interface, the power supply can be cut off.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design RESET 370–620 ms 4.7K Reset pulse 47K Figure 15: Reference Circuit of RESET by Using Driving Circuit S2 RESET TVS Close to S2 Figure 16: Reference Circuit of RESET by Using Button The reset scenario is illustrated in the following figure. VBAT 620 ms ≥ 370 ms VIH≥ 1.17 V RESET VIL≤ 0.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Please assure that there is no large capacitance on PWRKEY and RESET pins. 3.9. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM cards are supported. Table 11: Pin Definition of (U)SIM Interface Pin Name Pin No.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_EXT USIM_VDD 470K 10K 100 nF (U)SIM Card Connector USIM_VDD Module USIM_RST 22R USIM_CLK USIM_DET 22R USIM_DATA 22R VCC RST CLK GND VPP IO CD1 CD2 GND 33 pF 33 pF33 pF GND Figure 18: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET disconnected.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ ⚫ with surrounded ground. In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 10 pF. The 22 Ω resistors should be added in series between the module and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection. The 33 pF capacitors are used for filtering interference of EGSM900.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Test Points Minimize these stubs Module R1 NM_0R R2 NM_0R Connector USB_VBUS USB_VBUS L1 USB_DM USB_DM USB_DP USB_DP Close to Module GND GND ESD Array Figure 20: Reference Circuit of USB 2.0 Application USB_VBUS USB_VBUS USB_SS_TX_P C1 100 nF USB_SS_TX_M C2 100 nF USB_SS_RX_P USB_SS_RX_M USB_SS_RX_P C3 100 nF USB_SS_TX_P USB_SS_RX_M C4 100 nF USB_SS_TX_M Module AP Figure 21: Reference Circuit of USB 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ ⚫ Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. If a USB connector is used, please keep the ESD protection components as close to the USB connector as possible.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Can be configured to GPIOs BT_UART_RXD 63 DI BT UART receive BT_UART_RTS 61 DI BT UART request to send BT_UART_CTS 62 DO BT UART clear to send Table 15: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_TXD 107 DO Debug UART transmit 1.8 V power domain. DBG_RXD 110 DI Debug UART receive 1.8 V power domain. Table 16: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design attention to the direction of connection. 4.7K VDD_1V8 VDD_1V8 1 nF MCU/ARM Module 10K RXD TXD RXD TXD 10K VCC_MCU 1 nF VDD_1V8 4.7K RTS RTS CTS CTS GND GND Figure 23: Reference Circuit with Transistor Circuit NOTES 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design I2S_DOUT 261 DO I2S data out Table 18: Pin Definition of I2C Interface Pin Name Pin No. I/O Description Comment I2C1_SCL 79 OD I2C serial clock I2C1_SDA 80 OD I2C serial data Require external pull-up to 1.8 V. CDC_RST I2S_MCLK I2S_CLK I2S_WS I2S_DIN I2S_DOUT RESET MCLK BCLK WCLK DOUT DIN I2C1_SCL I2C1_SDA SCL SDA INP INN BIAS The following figure shows a reference design of I2S and I2C interfaces with an external codec IC.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design SDIO_VDD 60 PI SDIO power supply SDC1_DATA_0 49 IO SDIO data bit 0 SDC1_DATA_1 50 IO SDIO data bit 1 SDC1_DATA_2 51 IO SDIO data bit 2 SDC1_DATA_3 52 IO SDIO data bit 3 SDC1_CMD 48 IO SDIO command SDC1_DATA_4 53 IO SDIO data bit 4 SDC1_DATA_5 55 IO SDIO data bit 5 SDC1_DATA_6 56 IO SDIO data bit 6 SDC1_DATA_7 58 IO SDIO data bit 7 SDC1_CLK 47 DO SDIO clock EMMC_RST 54 DO eMMC reset EMMC_PWR_EN 45 D
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Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_1V8 R12 NM R13 NM R14 NM R15 NM R16 NM R17 NM R18 NM R19 NM R20 10K R21 47K VDD_1.8V SDC1_DATA_0 SDC1_DATA_1 SDC1_DATA_2 R1 0R DAT0 R2 0R VCCQ C12 100 nF DAT1 R3 0R C13 1 µF DAT2 VDD_3V SDC1_DATA_3 SDC1_DATA_4 SDC1_DATA_5 SDC1_DATA_6 SDC1_DATA_7 SDC1_CMD SDC1_CLK EMMC_RST EMMC_PWR_EN SDIO_VDD R4 0R DAT3 R5 0R VCC C14 100 nF DAT4 R6 0R C15 2.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.14. SPI Interfaces The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of SPI is up to 50 MHz. Table 20: Pin Definition of SPI Interfaces Pin Name Pin No. I/O Description Comment SPI1_CLK 216 DO SPI1 clock SPI1_CS 213 DO SPI1 chip select SPI1_MISO 219 DI SPI1 master-in salve-out SPI1_MOSI 210 DO SPI1 master-out slave-in 1.8 V power domain. Can be configured to GPIO.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design t(cl) SPI clock low-level time 9.0 - - ns t(mov) SPI master data output valid time -5.0 - 5.0 ns t(mis) SPI master data input setup time 5.0 - - ns t(mih) SPI master data input hold time 1.0 - - ns NOTE The module provides a 1.8 V SPI interface. A level translator should be used between the module and the host if customers’ application is equipped with a 3.3 V processor or device interface. 3.15.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bit 3 RGMII_PWR_EN 27 DO Enable external LDO to supply power to RGMII_PWR_IN 1.8 V power domain 1.8/2.5 V power supply input.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII_VDDO R13 R14 R15 R16 RGMII_MD_IO MDIO RGMII_MD_CLK MDC RGMII_INT INTN RGMII_RST RESETN R1 0R RGMII_RX_0 R2 0R RGMII_RX_1 R3 0R RGMII_RX_2 R4 0R RGMII_RX_3 R5 0R RGMII_CTL_RX R6 0R RGMII_CK_RX RGMII_TX_0 RGMII_TX_1 RGMII_TX_2 RGMII_TX_3 RGMII_CTL_TX RGMII_CK_TX R7 0R RXC RCLK TXD3 R11 0R RXC R12 0R RGMII_PWR_IN RXD3 TXD2 R10 0R RGMII_PWR_IN RXD2 TXD1 R9 0R RGMII_PWR_EN RXD1 TXD0 R8 0R RGMII_PWR_EN RX
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Automotive Module Series AG521R-NA QuecOpen Hardware Design The value of R1–R16 varies with the selection of PHY. 3.16. WLAN and BT Interfaces* The module provides a PCIe interface for WLAN function and UART & PCM interfaces for BT function. Table 23: Pin Definition of WLAN and BT Interfaces Pin Name Pin No.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design GPIOs.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_EXT R1 100K R2 100K PCIE_CLKREQ PCIE_CLKREQ_N PCIE_WAKE PCIE_WAKE PCIE_RST PCIE_RST PCIE_REFCLKP PCIE_REFCLK_P PCIE_REFCLKM PCIE_REFCLK_M PCIE_TX_M PCIE_TX_P C1 100 nF PCIE_RXM C2 100 nF PCIE_RXP C3 100 nF PCIE_RX_M C4 100 nF PCIE_RX_P PCIE_TXM PCIE_TXP COEX_UART_ RXD COEX_UART_ TXD COEX_UART_ TXD COEX_UART_ RXD BT_UART_TXD BT_UART_RXD BT_UART_RXD BT_UART_TXD BT_UART_RTS BT_UART_RTS BT_UART_CTS BT_UART_CTS PCM_S
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Automotive Module Series AG521R-NA QuecOpen Hardware Design The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications. ⚫ ⚫ ⚫ ⚫ ⚫ It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the differential impedance is 95 Ω ±10%.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ADC Sample Rate 4.8 MHz NOTES 1. 2. 3. The input voltage for each ADC interface must not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pins when VBAT is removed. It is recommended to use resistor divider circuit for ADC application. 3.18. USB_BOOT Interface The module provides a USB_BOOT pin.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 27: Pin Definition of GPIOs Pin Name Pin No. I/O GPIO1 100 IO GPIO2 101 IO GPIO3 102 IO GPIO4 104 IO GPIO5 116 IO GPIO6 243 IO GPIO7 246 IO GPIO8 249 DO Description Comment General-purpose input/output 1.8 V power domain. unused, keep them open.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 4 Antenna Interfaces The module includes one main antenna interface (ANT_MAIN) and one Rx-diversity antenna interface (ANT_DIV) which is used to resist the fall of signals caused by high speed movement and multipath effect. The antenna ports have an impedance of 50 Ω. 4.1. Main/Rx-diversity Antenna Interface 4.1.1. Pin Definition The pin definition of Main/Rx-diversity antenna interfaces are shown below.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-FDD B66 1710-1780 2110-2200 MHz LTE-FDD B12 699-716 729-746 MHz LTE-FDD B13 777-787 746-756 MHz LTE-FDD B14 788-798 758-768 MHz LTE-FDD B17 704-716 734-746 MHz LTE-FDD B26 814-849 859~894 MHz LTE-FDD B5 824~849 869~894 MHz LTE-FDD B30 / 2350-2360 MHz LTE-FDD B7 2500~2570 2620~2690 MHz LTE-FDD B71 663-698 617-652 MHz LTE-FDD B29 2 ) / 717-728 MHz NOTE 1. 1) LTE-FDD B29, B30 and B32 support Rx only.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Main Antenna Module R1 0R ANT_MAIN C1 C2 NM NM Diversity Antenna R2 0R ANT_DIV C3 C4 NM NM Figure 31: Reference Circuit of RF Antenna Interfaces NOTES ANT_DIV function is enabled by default. AT+QCFG="diversity",0 command can be used to disable receive diversity. See document [3] for details of the command. 4.1.4.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 33: Coplanar Waveguide Design on a 2-layer PCB Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫ ⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ ⚫ ⚫ ⚫ The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135°. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 4.2.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the HFM connector provided by Rosenberger. Figure 36: Description of the HFM Connector For more details, visit https://www.rosenbergerap.com.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 5 Reliability, Radio and Electrical Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 31: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 6.0 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 2.0 A Voltage at Digital Pins -0.3 2.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Parameter USB_VBUS Description Conditions VBAT_RF the minimum and maximum values. USB connection detection Min. Typ. Max. Unit 3.0 5.0 5.25 V 5.3. Operation and Storage Temperatures Table 33: Operation and Storage Temperatures Parameter Min. Typ. Max.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 34: Module Current Consumption (25 °C, 3.8 V Power Supply) Description Conditions Typ. Unit OFF state Power down 0.021 mA AT+CFUN=0 (USB disconnected) 1.144 mA WCDMA PF = 64 (USB disconnected) 2.69 mA WCDMA PF = 64 (USB suspend) TBD mA WCDMA PF = 128 (USB disconnected) 2.21 mA WCDMA PF = 256 (USB disconnected) 1.94 mA WCDMA PF = 512 (USB disconnected) 1.86 mA LTE-FDD PF = 32 (USB disconnected) 4.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design WCDMA voice call LTE-FDD B13 @ 23.0 dBm 543 mA LTE-FDD B14 @ 23.0 dBm 618 mA LTE-FDD B25 @ 23.0 dBm 650 mA LTE-FDD B26 @ 23.0 dBm 620 mA LTE-FDD B66 @ 23.0 dBm 630 mA LTE-FDD B71 @ 23.0 dBm 600 mA WCDMA B2 @ 23 dBm 574.09 mA WCDMA B4 @ 23 dBm 555.9 mA WCDMA B5 @ 23 dBm 555.31 mA 5.5. RF Output Power The following table shows the RF output power of the module. Table 35: RF Output Power Frequency Max. Min.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-TDD B25 23 dBm ±2 dB <- 39 dBm LTE-TDD B26 23 dBm ±2 dB <- 39 dBm LTE-TDD B66 23 dBm ±2 dB <- 39 dBm LTE-TDD B71 23 dBm ±2 dB <- 39 dBm 5.6. RF Receiving Sensitivity Table 36: RF Receiving Sensitivity (Unit: dBm) Receive Sensitivity (Typ.) Frequency Primary Diversity SIMO 3GPP (SIMO) WCDMA B2 -110 -111 -113.5 -106.7 dBm WCDMA B4 -110 -111 -113.5 -106.7 dBm WCDMA B5 -110.5 -111.5 -114 -103.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-TDD B71 (10 MHz) -100.5 -100.3 -103.5 -93.5 dBm 5.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design The following shows two kinds of heatsink designs for reference and customers can choose one or both of them according to their application structure.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 2. first returned value. For more detailed introduction on thermal design, see document [5].
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 6.1.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 40: Module Bottom Dimensions (Top View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 6.2. Recommended Footprint Figure 41: Recommended Footprint (Top View) NOTE For convenient maintenance of the module, please keep about 3 mm between the module and other components on the motherboard.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 6.3. Top and Bottom Views Figure 42: Top View of the Module Figure 43: Bottom View of the Module NOTE These are renderings of the module. For authentic appearance, see the module received from Quectel.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 7 Storage, Manufacturing and Packaging 7.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 1. 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to IPC/JEDEC J-STD-033.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150°C and 200°C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220°C) 45–70 s Max temperature 238–246 °C Cooling down slope -1.5 to -3 °C/s Reflow Cycle Max reflow cycle 1 7.3. Packaging The module is packaged in tape and reel carriers. One reel is 10.56 meters long and contains 220 modules.
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Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 45: Tape Specifications Figure 46: Reel Specifications AG521R-NA_QuecOpen_Hardware_Design 87 / 104
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Automotive Module Series AG521R-NA QuecOpen Hardware Design 8 Appendix A References Table 39: Related Documents SN Document Name Remark [1] Quectel_V2X&5G_EVB_User_Guide EVB User Guide for Automotive Modules [2] Quectel_AG52xR_Series_QuecOpen_Developer_Guide AG52xR Series QuecOpen Developer Guide [3] Quectel_AG52xR_Series _AT_Commands_Manual AG52xR Series AT Commands Manual [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_LTE_Module_Thermal_Design_Guide Therm
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Automotive Module Series AG521R-NA QuecOpen Hardware Design DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air DL Downlink DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge EVDO Evolution-Data Optimized FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GPS Glo
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Automotive Module Series AG521R-NA QuecOpen Hardware Design MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol Ppp Peak Pulse Power QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing TDMA Ti
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Automotive Module Series AG521R-NA QuecOpen Hardware Design VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Lo
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OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
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Antenna (1) The antenna must be installed such that 20 cm is maintained between the antenna and users, (2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product.
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Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
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This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
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Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
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Cet appareil est conçu uniquement pour les intégrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit être installée de telle sorte qu'une distance de 20 cm est respectée entre l'antenne et les utilisateurs, et 2) Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplémentaires sur l'émetteur ne seront pas nécessaires.
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Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.