BG770A-GL Hardware Design LPWA Module Series Version: 1.0.0 Date: 2021-01-28 Status: Preliminary www.quectel.
LPWA Module Series BG770A-GL Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
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LPWA Module Series BG770A-GL Hardware Design Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
LPWA Module Series BG770A-GL Hardware Design About the Document Revision History Version Date Author Description - 2021-01-28 Besson RONG/ Ben JIANG Creation of the document 1.0.
LPWA Module Series BG770A-GL Hardware Design Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ..........................................................................................................................................
LPWA Module Series BG770A-GL Hardware Design 3.16. ADC Interfaces* ........................................................................................................................ 47 3.17. GPIO Interfaces* ....................................................................................................................... 48 3.18. GRFC Interfaces* ...................................................................................................................... 49 4 GNSS Receiver*............
LPWA Module Series BG770A-GL Hardware Design Table Index Table 1: Special Mark................................................................................................................................. 13 Table 2: Frequency Bands and GNSS Types of BG770A-GL Module ...................................................... 14 Table 3: Key Features of BG770A-GL ....................................................................................................... 15 Table 4: Definition of I/O Parameters...
LPWA Module Series BG770A-GL Hardware Design Table 42: Recommended Thermal Profile Parameters ............................................................................. 74 Table 43: BG770A-GL Packaging Specifications ...................................................................................... 75 Table 44: Related Documents.................................................................................................................... 76 Table 45: Terms and Abbreviations ....................
LPWA Module Series BG770A-GL Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 17 Figure 2: Pin Assignment (Top View) ........................................................................................................ 20 Figure 3: Sleep Mode Application via UART .............................................................................................
LPWA Module Series BG770A-GL Hardware Design 1 Introduction This document defines BG770A-GL module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of the module. To facilitate application designs, it also includes some reference designs for customers’ reference.
LPWA Module Series BG770A-GL Hardware Design must not exceed: Operating Band LTE BAND 2 7.300 7.30 LTE BAND 4 4.300 4.30 LTE BAND 5 8.841 5.40 LTE BAND 12 8.098 4.91 LTE BAND 13 8.514 5.23 LTE BAND 25 7.300 7.30 LTE BAND 26(814-824) 8.841 5.36 LTE BAND 26(824-849) 8.841 5.36 LTE BAND 66 4.300 4.30 NB-IOT Band 2 7.300 7.30 NB-IOT Band 4 4.300 4.30 NB-IOT Band 5 8.841 5.40 NB-IOT Band 12 8.098 4.91 NB-IOT Band 25 7.300 4.93 NB-IOT Band 26 8.841 7.
LPWA Module Series BG770A-GL Hardware Design The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
LPWA Module Series BG770A-GL Hardware Design doit porter une étiquette indiquant le numéro de certification d'Innovation, Sciences et Développement économique Canada pour le module, précédé du mot «Contient» ou d'un libellé semblable exprimant la même signification, comme suit: "Contient IC: 10224A-2021BG770A " ou "où: 10224A-2021BG770A est le numéro de certification du module". 1.1.
LPWA Module Series BG770A-GL Hardware Design 2 Product Concept 2.1. General Description BG770A-GL is an embedded IoT (LTE Cat M1, LTE Cat NB1/Cat NB2*) wireless communication module. It provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also provides optional GNSS* and voice* 1) functionality to meet customers’ specific application demands. The module is based on an architecture in which WWAN (LTE) and GNSS Rx chains share certain hardware blocks.
LPWA Module Series BG770A-GL Hardware Design With a compact profile of 14.9 mm × 12.9 mm × 1.9 mm, BG770A-GL can meet almost all requirements for M2M applications such as smart metering, tracking system, security, wireless POS, etc. It is especially suitable for size and weight sensitive applications such as smart watch and other wearable devices. BG770A-GL is an SMD type module which can be embedded into applications through its 94 LGA pads. It supports internet service protocols like TCP, UDP and PPP.
LPWA Module Series BG770A-GL Hardware Design Debug UART: Used for firmware upgrade, software debugging and log output 115200 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Support RTS and CTS hardware flow control AUX UART: Used for RF calibration debugging and log output 921600 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control GNSS* GPS, GLONASS AT Comm
LPWA Module Series BG770A-GL Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of BG770A-GL and illustrates the major functional parts. Power management Baseband Radio frequency Peripheral interfaces Figure 1: Functional Diagram NOTE PCM and I2C interfaces are for VoLTE* only.
LPWA Module Series BG770A-GL Hardware Design 2.4. Evaluation Board To facilitate application development with BG770A-GL conveniently, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cables, USB data cables, earphone, antennas and other peripherals to control or test the module. For more details, see document [2].
LPWA Module Series BG770A-GL Hardware Design 3 Application Interfaces BG770A-GL is equipped with 94 LGA pads that can be connected to customers’ cellular application platforms.
LPWA Module Series BG770A-GL Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG770A-GL.
LPWA Module Series BG770A-GL Hardware Design NOTES 1. 2. 3. 4. 5. ADC input voltage must not exceed 1.8 V. The input voltage range of USB_VBUS is 1.19–2.0 V. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. PCM and I2C interfaces are for VoLTE* only. 3.2. Pin Description The following tables show the pin definition of BG770A-GL.
LPWA Module Series BG770A-GL Hardware Design Table 5: Pin Description Power Supply Pin Name VBAT_BB Pin No. 19 I/O Description DC Characteristics Comment PI Power supply for the module’s baseband part Vmax = 4.35 V Vmin = 2.2 V Vnom = 3.3 V Refer to NOTE 1 Vmax = 4.2 V Vmin = 3.1 V Vnom = 3.3 V Refer to NOTE 1 Vnom = 1.8 V IOmax = 50 mA If this pin is unused, keep it open. VBAT_RF 20 PI Power supply for the module’s RF part VDD_EXT 21 PO Provide 1.
LPWA Module Series BG770A-GL Hardware Design Compliant with USB 2.0 standard specification. Require differential impedance of 90 Ω. USB_DP 11 DIO USB differential data (+) USB_DM 10 DIO USB differential data (-) USBPHY_3P3 42 PI Power supply for USB PHY circuit Vnom = 3.3 V 64 DO/PU External LDO enable control for USB 1.8 V Pin Name Pin No. I/O Description DC Characteristics Comment USIM_DET* 44 DI/PD (U)SIM card hot-plug detect 1.8 V If this pin is unused, keep it open.
LPWA Module Series BG770A-GL Hardware Design Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics DBG_RXD 61 DI/PU Debug UART receive 1.8 V DBG_TXD 60 DO/PU Debug UART transmit 1.8 V DBG_CTS 51 DO/PU Debug UART clear to send 1.8 V DBG_RTS 92 DI/PD Debug UART request to send 1.8 V Comment If this pin is unused, keep it open. Auxiliary UART Interface Pin Name Pin No. I/O Description DC Characteristics AUX_TXD 93 DO/PU Auxiliary UART transmit 1.
LPWA Module Series BG770A-GL Hardware Design I2C_SDA 5 OD I2C serial data (for external codec) External pull-up resistor is required. 1.8 V only. If this pin is unused, keep it open. Antenna Interfaces DC Characteristics Pin Name Pin No. I/O Description ANT_MAIN 26 AIO Main antenna interface 50 Ω impedance. 32 AI GNSS antenna interface 50 Ω impedance. If this pin is unused, keep it open. Pin Name Pin No.
LPWA Module Series BG770A-GL Hardware Design Other Interface Pins Pin Name Pin No. I/O Description DC Characteristics Comment W_DISABLE#* 41 DI/PU Airplane mode control 1.8 V Pulled up by default. When it is at low voltage level, the module can enter airplane mode. If this pin is unused, keep it open. AP_READY* 77 DI/PU Application processor ready 1.8 V If this pin is unused, keep it open. PON_TRIG* 72 DI/NP Wake up the module from PSM 1.
LPWA Module Series BG770A-GL Hardware Design 3.3. Operating Modes The table below briefly summarizes the various operating modes of BG770A-GL. Table 6: Overview of Operating Modes Mode Normal Operation Details Connected The module is connected to network. Its current consumption varies with the network setting and data transfer rate. Idle The module remains registered on network, and is ready to send and receive data. In this mode, the software is active.
LPWA Module Series BG770A-GL Hardware Design 3.4. Power Saving 3.4.1. Airplane Mode When the module enters airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. This mode can be set via the following ways. Hardware: W_DISABLE#* is pulled up by default. Driving it low will let the module enter airplane mode. Software: AT+CFUN= provides choice of the functionality level, through setting into 0, 1 or 4.
LPWA Module Series BG770A-GL Hardware Design NOTE See document [4] for details about AT+CPSMS. 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value.
LPWA Module Series BG770A-GL Hardware Design The following figure shows the connection between the module and the host. Figure 3: Sleep Mode Application via UART When BG770A-GL has a URC to report, MAIN_RI signal will wake up the host. See Chapter 3.14 for details about MAIN_RI behavior. Driving the MAIN_DTR low will wake up the module. AP_READY* will detect the sleep state of the host (can be configured to high voltage level or low voltage level detection).
LPWA Module Series BG770A-GL Hardware Design NOTE 1) When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 3.5.2. Decrease Voltage Drop The power supply VBAT_BB range of BG770A-GL is from 2.2 V to 4.35 V, the power supply VBAT_RF range of BG770A-GL is from 3.1 V to 4.2 V. When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V.
LPWA Module Series BG770A-GL Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Pin Definition of PWRKEY The following table shows the pin definition of PWRKEY. Table 8: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment PWRKEY* 46 Turn on/off the module VILmax = 0.3 V VIHmin = 1.0 V Internally pulled up resistor is 470 kΩ. 3.6.2. Turn on Module Using PWRKEY When the module is in power off mode, it can be turned on by driving PWRKEY low for at least 500 ms.
LPWA Module Series BG770A-GL Hardware Design Figure 6: Turn on the Module by Using Keystroke The power-up scenario is illustrated in the following figure.
LPWA Module Series BG770A-GL Hardware Design NOTE Ensure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms. 3.6.3. Turn off Module Either of the following methods can be used to turn off the module normally: Turn off the module through PWRKEY. Turn off the module through AT+QPOWD. 3.6.3.1.Turn off Module through PWRKEY Drive the PWRKEY pin low for 650–1500 ms and then releasing it, the module will execute power-down procedure.
LPWA Module Series BG770A-GL Hardware Design 3.7. Reset the Module RESET_N is used to reset the module. The module can be reset by driving RESET_N low for minimum assertion time 100 ms. Table 9: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics RESET_N 45 Reset the module VILmax = 0.3 V VIHmin = 1.3 V Comment The reset timing is illustrated in the following figure. Figure 9: Reset Timing The recommended circuit is similar to the PWRKEY control circuit.
LPWA Module Series BG770A-GL Hardware Design Figure 11: Reference Circuit of RESET_N by Using Button NOTE Ensure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG* BG770A-GL provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects high level for minimum assertion time 100 μs, the module will wake up from PSM. Table 10: Pin Definition of PON_TRIG Pin Name PON_TRIG Pin No.
LPWA Module Series BG770A-GL Hardware Design A reference circuit is shown in the following figure. Figure 12: Reference Circuit of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG770A-GL supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 11: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET* 44 DI/PD (U)SIM card hot-plug detect 1.8 V power domain.
LPWA Module Series BG770A-GL Hardware Design BG770A-GL supports (U)SIM card hot-plug via USIM_DET, and both high- and low- level detections are supported. The function is disabled by default, and see AT+QSIMDET in document [4] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET unconnected.
LPWA Module Series BG770A-GL Hardware Design Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential.
LPWA Module Series BG770A-GL Hardware Design The following figures illustrate reference designs of USB PHY and USB interface. U1 VIN VBAT C1 1uF VDD_EXT USBPHY_3P3_EN R1 10K R2 0R EN VOUT GND SGM2040-3.3 USBPHY_3P3 C2 1uF Figure 15: Reference Design of USB PHY Figure 16: Reference Design of USB Interface To ensure the integrity of USB data trace signal, components R3 and R4 should be placed close to the module, and also these resistors should be placed close to each other.
LPWA Module Series BG770A-GL Hardware Design attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection devices as close to the USB connector as possible. NOTES 1. The USB interface is under development, it is not recommended to use at present. 2. The input voltage range of USB_VBUS is 1.19–2.0 V. 3.11.
LPWA Module Series BG770A-GL Hardware Design MAIN_RI* 76 DO/PU Main UART ring indication NOTE AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command can be used to set the hardware flow control (the function is disabled by default). See document [4] for more details about these AT commands. Table 14: Pin Definition of Debug UART Interface Pin Name Pin No.
LPWA Module Series BG770A-GL Hardware Design Figure 17: Main UART Reference Design (Translator Chip) Visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. For the design of circuits in dotted lines, refer to that of circuits in solid lines, but pay attention to the direction of connection. Figure 18: Main UART Reference Design (Transistor Circuit) NOTES 1.
LPWA Module Series BG770A-GL Hardware Design 3.12. PCM and I2C Interfaces* BG770A-GL provides one Pulse Code Modulation (PCM) digital interface and one I2C interface for VoLTE only. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description PCM_CLK 3 DO/PD PCM clock PCM_SYNC 35 DO/PU PCM data frame sync Comment 1.
LPWA Module Series BG770A-GL Hardware Design 3.13. Network Status Indication* BG770A-GL provides one network status indication pin: NET_STATUS. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NET_STATUS in different network activity status. Table 17: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 79 DO/PU Indicate the module's network activity status 1.8 V power domain.
LPWA Module Series BG770A-GL Hardware Design 3.14. STATUS The STATUS pin is used to indicate the operation status of BG770A-GL. It outputs high level when the module powers on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 78 DO/PD Indicate the module's operation status 1.8 V power domain The following figure shows a reference circuit of STATUS. Figure 21: Reference Design of STATUS 3.15.
LPWA Module Series BG770A-GL Hardware Design The default MAIN_RI behaviors can be configured flexibly by AT+QCFG="urc/ri/ring"* command. For more details about AT+QCFG, see document [3]. NOTE A URC can be outputted from UART port, through configuration via AT+QURCCFG. 3.16. ADC Interfaces* The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 can be used to read the voltage value on ADC0 pin. AT+QADC=1 be used to read the voltage value on ADC1 pin.
LPWA Module Series BG770A-GL Hardware Design NOTES 1. 2. 3. ADC input voltage must not exceed 1.8 V. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the divider’s resistor accuracy should be no less than 1 %. 3.17. GPIO Interfaces* The module provides seven general-purpose input and output (GPIO) interfaces. AT+QCFG="gpio" can be used to configure the status of GPIO pins.
LPWA Module Series BG770A-GL Hardware Design 3.18. GRFC Interfaces* The module provides two generic RF control interfaces for the control of external antenna tuners. Table 24: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 83 Generic RF controller 1.8 V power domain. GRFC2 94 Generic RF controller 1.8 V power domain.
LPWA Module Series BG770A-GL Hardware Design 4 GNSS Receiver* 4.1. General Description BG770A-GL supports GPS and GLONASS satellite systems using dedicated hardware accelerators in a power and cost-efficient manner. The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via debug UART interface by default. By default, BG770A-GL GNSS engine is switched off. It has to be switched on via AT command.
LPWA Module Series BG770A-GL Hardware Design Hot start @ open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @ open sky 1.41 m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
LPWA Module Series BG770A-GL Hardware Design 5 Antenna Interfaces BG770A-GL includes a main antenna interface and a GNSS antenna interface. The impedance of antenna port is 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below. Table 27: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 26 AIO Main antenna interface 50 Ω impedance 5.1.2.
LPWA Module Series BG770A-GL Hardware Design LTE-FDD B13 777–787 746–756 MHz LTE-FDD B17 1) 704–716 734–746 MHz LTE-FDD B18 815–830 860–875 MHz LTE-FDD B19 830–845 875–890 MHz LTE-FDD B20 832–862 791–821 MHz LTE-FDD B25 1850–1915 1930–1995 MHz LTE-FDD B26 2) 814–849 859–894 MHz LTE-FDD B27 2) 807–824 852–869 MHz LTE-FDD B28 703–748 758–803 MHz LTE-FDD B66 1710–1780 2110–2180 MHz NOTES 1. 2. 1) 2) LTE-FDD B17 is supported by Cat NB2 only.
LPWA Module Series BG770A-GL Hardware Design 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. 5.2.1. Pin Definition Table 29: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 32 AI GNSS antenna interface 50 Ω impedance 5.2.2. GNSS Operating Frequency Table 30: GNSS Operating Frequency Type Frequency Unit GPS 1575.42 ±1.023 MHz GLONASS 1597.5–1605.8 MHz 5.2.3.
LPWA Module Series BG770A-GL Hardware Design NOTE The module of BG770A-GL is designed with a passive antenna. 5.3. Antenna Installation 5.3.1. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the clearance between RF traces and grounds (S).
LPWA Module Series BG770A-GL Hardware Design Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
LPWA Module Series BG770A-GL Hardware Design For more details about RF layout, see document [5]. 5.3.2. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 31: Antenna Requirements Antenna Type Requirements GNSS 1) Frequency range: 1559–1609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.
LPWA Module Series BG770A-GL Hardware Design 5.3.3. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connectors provided by HIROSE. Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 29: Mechanicals of U.
LPWA Module Series BG770A-GL Hardware Design The following figure describes the space factor of mated connector. Figure 30: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com.
LPWA Module Series BG770A-GL Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 32: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.2 4.5 V VBAT_RF / 4.6 V USB_VBUS 1.19 2.0 V Voltage at Digital Pins -0.3 2.0 V 6.2.
LPWA Module Series BG770A-GL Hardware Design the minimum and maximum values. USBPHY_3P3 Power supply for USB PHY circuit USB_VBUS USB connection detect 3.3 1.19 V 2.0 V NOTE 1) When the module starts up normally, in order to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 6.3. Operating and Storage Temperatures The operating and storage temperatures of the module are listed in the following table.
LPWA Module Series BG770A-GL Hardware Design 6.4. Current Consumption The following table shows current consumption of BG770A-GL. Table 35: BG770A-GL Current Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage Power-off @ USB/UART disconnected TBD - μA PSM PSM @ USB/UART disconnected TBD - μA Rock Bottom AT+CFUN=0 @ Sleep mode TBD - mA LTE Cat M1 DRX = 1.28 s TBD - mA LTE Cat NB1 DRX = 1.28 s TBD - mA LTE Cat M1 e-I-DRX = 81.
LPWA Module Series BG770A-GL Hardware Design LTE Cat NB2 data transfer (GNSS OFF) LTE-FDD B12 @ dBm TBD TBD mA LTE-FDD B13 @ dBm TBD TBD mA LTE-FDD B18 @ dBm TBD TBD mA LTE-FDD B19 @ dBm TBD TBD mA LTE-FDD B20 @ dBm TBD TBD mA LTE-FDD B25 @ dBm TBD TBD mA LTE-FDD B26 @ dBm TBD TBD mA LTE-FDD B27 @ dBm TBD TBD mA LTE-FDD B28A @ dBm TBD TBD mA LTE-FDD B28B @ dBm TBD TBD mA LTE-FDD B66 @ dBm TBD TBD mA LTE-FDD B1 @ dBm TBD TBD mA LTE-FDD B2 @ dBm TBD TBD mA
LPWA Module Series BG770A-GL Hardware Design LTE-FDD B66 @ dBm TBD TBD mA Table 36: GNSS Current Consumption (Power Supply: 3.3 V, Room Temperature) Description Searching (AT+CFUN=0) Tracking (AT+CFUN=0) Conditions Typ. Unit Cold start @ Instrument TBD mA Hot start @ Instrument TBD mA Lost state @ Instrument TBD mA Instrument environment @ Passive antenna TBD mA Half sky @ Real network, Passive antenna TBD mA Half sky @ Real network, Active antenna TBD mA 6.5.
LPWA Module Series BG770A-GL Hardware Design VOH Output high voltage 1.36 2.0 V VOL Output low voltage 0 0.38 V 6.6. RF Output Power The following table shows the RF output power of BG770A-GL. Table 39: BG770A-GL RF Output Power Frequency Bands Max. RF Output Power Min. RF Output Power LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/B171)/B18/B19 /B20/B25/B26 2)/B27 2) /B28/B66 23 dBm ±2.7 dB < -39 dBm NOTES 1. 2. 1) 2) LTE-FDD B17 is supported by Cat NB2 only.
LPWA Module Series BG770A-GL Hardware Design LTE-FDD B5 TBD/-100.8 TBD/-107.5 LTE-FDD B8 TBD/-99.8 TBD/-107.5 LTE-FDD B12 TBD/-99.3 TBD/-107.5 LTE-FDD B13 TBD/-99.3 TBD/-107.5 LTE-FDD B17 2) Not Supported TBD/-107.5 LTE-FDD B18 TBD/-102.3 TBD/-107.5 LTE-FDD B19 TBD/-102.3 TBD/-107.5 LTE-FDD B20 TBD/-99.8 TBD/-107.5 LTE-FDD B25 TBD/-100.3 TBD/-107.5 LTE-FDD B26 3) TBD/-100.3 Not Supported LTE-FDD B27 3) TBD/-100.8 Not Supported LTE-FDD B28 TBD/-100.8 TBD/-107.
LPWA Module Series BG770A-GL Hardware Design 6.8. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of BG770A-GL module.
LPWA Module Series BG770A-GL Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1.
LPWA Module Series BG770A-GL Hardware Design Pin 1 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard.
LPWA Module Series BG770A-GL Hardware Design 7.2. Recommended Footprint Figure 33: Recommended Footprint (Top View) NOTES 1. 2. 3. For easy maintenance of the module, keep a distance of about 3 mm between the module and other components on the motherboard. All reserved pins must be kept open. For stencil design requirements of the module, see document [6].
LPWA Module Series BG770A-GL Hardware Design 7.3. Top and Bottom Views Figure 34: Top and Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, refer to the module received from Quectel.
LPWA Module Series BG770A-GL Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
LPWA Module Series BG770A-GL Hardware Design NOTES 1. 1)This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed.
LPWA Module Series BG770A-GL Hardware Design Table 42: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1 to 3 °C/s Soak time (between A and B: 150 °C and 200 °C) 70 to 120 s Reflow Zone Max slope 2 to 3 °C/s Reflow time (D: over 220 °C) 45 to 70 s Max temperature 238 to 246 °C Cooling down slope -1.
LPWA Module Series BG770A-GL Hardware Design Figure 36: Tape Dimensions Figure 37: Reel Dimensions Table 43: BG770A-GL Packaging Specifications MOQ for MP Minimum Package: 500 Minimum Package x 4 = 2000 500 Pieces Size: 370 mm × 350 mm × 56 mm N.W: TBD G.W: TBD Size: 380 mm × 250 mm × 365 mm N.W: TBD G.
LPWA Module Series BG770A-GL Hardware Design 9 Appendix A References Table 44: Related Documents SN Document Name Description [1] Quectel_BG770A-GL_GNSS_Application_Note BG770A-GL GNSS Application Note [2] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide [3] Quectel_BG770A-GL_QCFG_AT_Commands_Manual AT+QCFG Commands Manual for BG770A-GL Module [4] Quectel_BG770A-GL_AT_Commands_Manual AT Commands Manual of BG770A-GL Module [5] Quectel_RF_Layout_Application_Note RF Layout Applicatio
LPWA Module Series BG770A-GL Hardware Design e-I-DRX Extended Idle Mode Discontinuous Reception EPC Evolved Packet Core ESD Electrostatic Discharge FDD Frequency Division Duplex HSS Home Subscriber Server I2C Inter-Integrated Circuit LNA Low Noise Amplifier LPF Low Pass Filter LTE Long Term Evolution MO Mobile Originated MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol PSM Power Saving Mode
LPWA Module Series BG770A-GL Hardware Design Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VSWR Voltage Standing Wave Ratio WWAN Wireless Wide Area Network BG770A-GL_Hardware_Design 78 / 75
