BG952A-GL QuecOpen Hardware Design LPWA Module Series Version: 1.0.0 Date: 2022-04-30 Status: Preliminary www.quectel.
LPWA Module Series Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
LPWA Module Series Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright © Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. Hereby, [Quectel Wireless Solutions Co.
LPWA Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.
LPWA Module Series metal powders.
LPWA Module Series About the Document Revision History Version Date Author Description - 2022-04-30 Arvin WU/ Ben JIANG Creation of the document 1.0.
LPWA Module Series Contents Safety Information ........................................................................................................................................ 3 About the Document .................................................................................................................................... 5 Contents .........................................................................................................................................................
LPWA Module Series 3.18. 3.19. 4 GNSS Receiver .................................................................................................................................... 46 4.1. 4.2. 4.3. 5 STATUS .....................................................................................................................................44 GRFC Interfaces* ......................................................................................................................45 General Description .......
LPWA Module Series Table Index Table 1: Special Mark ...................................................................................................................................11 Table 2: Frequency Bands and GNSS Types of BG952A-GL QuecOpen ..................................................12 Table 3: Key Features of BG952A-GL QuecOpen ...................................................................................... 13 Table 4: Definition of I/O Parameters .....................................
LPWA Module Series Table 42: Terms and Abbreviations .............................................................................................................
LPWA Module Series Figure Index Figure 1: Functional Diagram of BG952A-GL ............................................................................................. 15 Figure 2: Pin Assignment (Top View) .......................................................................................................... 18 Figure 3: Power Supply Limits during Burst Transmission ......................................................................... 28 Figure 4: Star Structure of the Power Supply ................
LPWA Module Series 1 Introduction QuecOpen® is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the advantages of QuecOpen® solution, especially the advantage in reducing product cost. With QuecOpen® solution, development flow for wireless applications and hardware designs will be simplified.
LPWA Module Series 2 Product Concept 2.1. General Description As an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module, it provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS function to meet your specific application demands. The module is based on an architecture in which WWAN (LTE) and GNSS Rx chains share certain hardware blocks.
LPWA Module Series pins. With a compact profile of 23.6 mm × 19.9 mm × 2.2 mm, it can meet almost all requirements for M2M applications such as security, smart metering, tracking system, and wireless POS. 2.2. Key Features Table 3: Key Features of BG952A-GL QuecOpen Features Details Power Supply Transmitting Power Class 3 (23 dBm ±2.7 dB) for LTE HD-FDD bands LTE Features Supply voltage: 2.2–4.35 1) V Typical supply voltage: 3.
LPWA Module Series 115200 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit)115200 bps baud rate by default CLI UART 2: Used for firmware upgrade, software debugging, log output, GNSS data and NMEA sentence output Supports RTS and CTS hardware flow control Default frame format: 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control SPI Interfaces Supports 3 SPI interfaces, 2 SPI master and 1 SPI slave, which can be multip
LPWA Module Series 1. When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/μs. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms. 2. 2) Within the operating temperature range, the module meets 3GPP specifications. 3.
LPWA Module Series 2.4. Evaluation Board To facilitate application design with the module conveniently, Quectel supplies the evaluation board (LTE OPEN EVB), a USB to RS-232 converter cable, a micro-USB cable, an earphone, antennas and other peripherals to control or test the module. For more details, see document [2].
LPWA Module Series 3 Application Interfaces 3.1. General Description BG952A-GL QuecOpen is equipped with 102 LGA pins.
LPWA Module Series 3.2. Pin Assignment The following figure shows the pin assignment of the module.
LPWA Module Series NOTES 1. 2. 3. 4. 5. ADC input voltage must not exceed 1.8 V. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. On BG952A-GL, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected. 3.
LPWA Module Series Table 5: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No. 32 33 I/O Description PI Power supply for the module’s baseband part PI Power supply for the module’s RF part PO Provide 1.8 V for external circuits DC Characteristics Vmax = 4.35 V Vmin = 2.2 V Vnom = 3.3 V Vnom = 1.8 V IOmax = 50 mA Comment See NOTE 1. See NOTE 1 Power supply for external GPIO’s pull-up circuits. If unused, keep these pins open.
LPWA Module Series VILmin = -0.2 V VILmax = 0.3 V VIHmin = 1 V VIHmax = 1.98 V 1.8 V power domain. If unused, keep these pins open. 96 DI Used to wake up the MCU in low power mode Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS 8 AI USB connection detect Vnom = 5.0 V Typical 5.0 V USB_DP 9 AIO USB differential data (+) Vmax = 4.1 V Vmin = -0.2 V Compliant with USB 2.0 standard specification. Require differential impedance of 90 Ω.
LPWA Module Series MAIN_TXD MAIN_CTS 35 36 DO Main UART transmit Can be configured as GPIOs. DO DTE clear to send signal from DCE (Connect to DTE’s CTS) VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V MAIN_RTS 37 DI DTE request to send signal from DCE (Connect to DTE’s RTS) MAIN_DCD 38 DO Main UART data carrier detect MAIN_RI 39 DO Main UART ring indication I/O Description DC Characteristics DI CLI UART2 receive VILmin = -0.
LPWA Module Series ADC1 2 AI General-purpose ADC interface Voltage range: 0.1–1.8 V ADC0 24 AI General-purpose ADC interface Voltage range: 0.1–1.8 V If unused, keep these pins open. Can be configured as GPIOs. I/O Description DC Characteristics Comment Other Interfaces Pin Name W_DISABLE # Pin No. 18 Airplane mode control DI VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V AP_READY* 19 DI Application processor ready 1.8 V power domain. Pulled up by default.
LPWA Module Series LNA power supply RESERVED Pins Pin Name Pin No. I/O Description DC Characteristics RESERVED 11–14, 16, 52,53, 56,57, 63, 75–78, 92,93,97,98 Comment Keep these pins open. GPIO Interfaces Pin Name Pin No.
LPWA Module Series NOTES 1. When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/μs. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms. 2. On BG950A-GL/BG951A-GL, PWRKEY is pulled up to an internal voltage of the baseband chipset inside the module, and the minimum high-level output voltage is 1.0 V. 3.
LPWA Module Series Sleep Mode The module remains the ability to receive paging message, SMS and TCP/UDP data from the network normally. In this mode, the current consumption is reduced to a low level. Power OFF Mode The module’s power supply is shut down by its power management unit. In this mode, the software is inactive, the serial interfaces are inaccessible, while the operating voltage (connected to VBAT_RF and VBAT_BB) remains applied.
LPWA Module Series 4. Upgrade firmware via CLI UART interface. NOTE 1. In recovery mode, pin 25 functions as CLI_RTS and pin 26 functions as CLI_CTS, while in other modes they are GPIO pins. 2. Since the baud rate of the serial port required to download firmware to the baseband chip is 3 Mbps, the flow control pins of the CLI serial port need to be reserved. Otherwise, you can only download with a 921600 baud rate, which is very slow.
LPWA Module Series 3.7. Power Supply 3.7.1. Power Supply Pins The module provides two VBAT pins for connection with an external power supply. The following table shows the details of VBAT_BB and VBAT_RF pins and ground pins. Table 9: Power Supply Pin Definition Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_BB 32 Power supply for the module’s baseband part 2.2 3.3 4.35 V VBAT_RF 33 Power supply for the module’s RF part 2.2 3.3 4.
LPWA Module Series recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 0.6 mm, and the width of VBAT_RF trace should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it should be.
LPWA Module Series Table 10: PWRKEY Pin Definition Pin Name Pin No. I/O Description PWRKEY 15 DI Turn on/off module Comment the Internally pulled up with a 470 kΩ resistor. When the module is in power-off mode, it can be turned on by driving PWRKEY low for 500–1000 ms. It is recommended to use an auto power-on circuit to control PWRKEY, as shown below. Figure 5: Auto Power-on Circuit Visit https://www.torexsemi.com for more information on the XC6119 voltage detector.
LPWA Module Series Figure 6: Turn on the Module with a Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the button, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module with a Button The power-up scenario is illustrated in the following figure.
LPWA Module Series Figure 8: Power-up Timing NOTES Ensure that VBAT is stable before pulling down PWRKEY and keep the interval no less than 100 ms. 3.8.2. Turn off Module After the module is turned off or enters PSM, do not pull up any I/O pin of the module. Otherwise, the module will have additional power consumption and may have damaged pins. 3.8.2.1.
LPWA Module Series Figure 9: Power-down Timing (PWRKEY) 3.9. Reset the Module The module can be reset by driving RESET_N low for at least 100 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 11: Pin Definition of RESET_N Pin Name Pin No. I/O Description RESET_N 45 DI Reset the module. Internally pulled up with a 470 kΩ resistor.
LPWA Module Series Figure 10: Reference Circuit of RESET_N with a Driving Circuit Another way to control the RESET_N is by using a button directly. Figure 11: Reference Circuit of RESET_N with a Button The reset scenario is illustrated in the following figure.
LPWA Module Series NOTE Make sure that there is no large capacitance on RESET_N. 3.10. PON_TRIG Interface BG952A-GL QuecOpen provides one PON_TRIG pin. Drive PON_TRIG is used to wake up the internal MCU. PON_TRIG is not pulled up/down internally by default. Table 12: Pin Definition of PON_TRIG Interface Pin Name Pin No. I/O Description Comment PON_TRIG 96 DI Used to wake up the MCU in low power mode 1.8 V power domain. Pulled down by default. PON_TRIG is used to wake up the internal MCU.
LPWA Module Series 3.11. (U)SIM Interface The module supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 13: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET 42 DI (U)SIM card hot-plug detect 1.8 V power domain. USIM_VDD 43 PO (U)SIM card power supply Only 1.8 V (U)SIM card is supported. USIM_RST 44 DO (U)SIM card reset 1.8 V power domain. USIM_DATA 45 DIO (U)SIM card data 1.
LPWA Module Series If (U)SIM card detection function is not needed, keep USIM_DET unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 15: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in (U)SIM circuit design: Keep the placement of (U)SIM card connector as close to the module as possible.
LPWA Module Series 3.12. USB Interface* BG952A-GL QuecOpen provides one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports full speed mode only. The following table shows the pin definition of USB interface. Table 14: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS 8 AI USB connection detect Typical 5.
LPWA Module Series Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data lines, so pay attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF.
LPWA Module Series MAIN_RI* 39 DO Main UART ring indication Table 16: Pin Definition of CLI UART Interface Pin Name Pin No. I/O Description Comment CLI_TXD2 95 DO CLI UART2 transmission CLI_RXD2 94 DI CLI UART2 reception 1.8 V power domain. If unused, keep them open. CLI_TXD1 27 DO CLI UART1 transmission CLI_RXD1 28 DI CLI UART1 reception 1.8 V power domain. If unused, keep them open. The module provides 1.8 V UART interfaces.
LPWA Module Series Figure 18: Main UART Reference Design (Transistor Circuit) NOTE 1. 2. 3. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. The UART interface should be disconnected in PSM and power off modes. Otherwise, the module will have additional power consumption and may have damaged pins. It is recommended to use a level-shifting chip without internal pull-up, such as TXB0108PWR, for voltage level translation. 3.14.
LPWA Module Series Figure 19: Reference Design of I2C Interface with an External I2C Interface Sensor 3.15. SPI Interfaces* The module provides three SPI interfaces. 2 SPI interfaces for master mode, 1 SPI interface for slave mode. The SPI interfaces function is multiplexed from GPIOs. SPIM0 and SPIM1 interfaces in master mode up to 25 MHz. SPIS interface supports slave mode only, up to 25 MHz. NOTE The power domain of the SPI interface is 1.8 V.
LPWA Module Series ADC0 24 AI General-purpose ADC interface ADC1 2 AI General-purpose ADC interface If unused, keep these pins open. Can be configured as GPIOs. The following table describes characteristics of ADC interfaces. Table 18: Characteristics of ADC Interfaces Parameter Min. Typ. Max. Unit Voltage Range 0 - 1.8 V Resolution 6 - 12 bit NOTES 1. ADC input voltage must not exceed 1.8 V. 2. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 3.
LPWA Module Series Table 20: Operating Status of NET_STATUS Pin Name NET_STATUS Indicator Status (Logic Level Changes) Network Status Flicker slowly (200 ms High/1800 ms Low) Network searching Flicker slowly (1800 ms High/200 ms Low) Idle Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling A reference design is shown in the following figure. Figure 20: Reference Design of NET_STATUS 3.18.
LPWA Module Series Figure 21: Reference Design of STATUS 3.19. GRFC Interfaces* The module provides two generic RF control interfaces for the control of external antenna tuners. Table 22: Pin Definition of GRFC Interfaces Pin Name Pin No. I/O Description GRFC1 83 DO Generic RF controller GRFC2 84 DO Generic RF controller Comment 1.8 V power domain. If unused, keep these pins open.
LPWA Module Series 4 GNSS Receiver 4.1. General Description BG952A-GL QuecOpen supports GPS and GLONASS satellite systems using dedicated hardware accelerators in a power and cost-efficient manner. The module supports standard NMEA-0183 protocol, and outputs GNSS NMEA sentences at 1 Hz data update rate via CLI UART interface by default. By default, BG772A-GL QuecOpen GNSS engine is switched off. It has to be switched on via AT command. The module does not support concurrent operation of WWAN and GNSS.
LPWA Module Series Accuracy (GNSS) CEP-50 XTRA enabled TBD s Autonomous @ open sky 1.41 m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
LPWA Module Series 5 Antenna Interfaces The module includes a main antenna interface and a GNSS antenna interface. The impedance of antenna ports is 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below. Table 25: Pin Definition of the Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 AIO Main antenna interface 50 Ω impedance 5.1.2.
LPWA Module Series LTE HD-FDD B13 777–787 746–756 MHz 704–716 734–746 MHz LTE HD-FDD B18 815–830 860–875 MHz LTE HD-FDD B19 830–845 875–890 MHz LTE HD-FDD B20 832–862 791–821 MHz LTE HD-FDD B25 1850–1915 1930–1995 MHz 814–849 859–894 MHz LTE HD-FDD B27 5 807–824 852–869 MHz LTE HD-FDD B28 703–748 758–803 MHz LTE HD-FDD B66 1710–1780 2110–2180 MHz LTE HD-FDD B17 LTE HD-FDD B26 4 5 5.1.3.
LPWA Module Series 5.2. GNSS Antenna Interface 5.2.1. Pin Definition Table 27: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 49 AI GNSS antenna interface 50 Ω impedance 5.2.2. GNSS Operating Frequency Table 28: GNSS Operating Frequency Type Frequency Unit GPS 1575.42 ±1.023 MHz GLONASS 1597.5–1605.8 MHz 5.2.3. Reference Design A reference design of GNSS antenna interface is shown as below.
LPWA Module Series 5.3. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
LPWA Module Series Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
LPWA Module Series For more details about RF layout, see document [6]. 5.4. Antenna Installation 5.4.1. Antenna Requirements Table 29: Antenna Requirements Antenna Type Requirements GNSS Frequency range: 1559–1609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi LTE VSWR: ≤ 2 Efficiency: > 30 % Max. Input Power: 50 W Input Impedance: 50 Ω Cable Insertion Loss: < 1 dB: LB (< 1 GHz) < 1.5 dB: MB (1–2.3 GHz) 5.4.2.
LPWA Module Series Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 29: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connectors.
LPWA Module Series For more details, visit http://www.hirose.com.
LPWA Module Series 6 Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.2 4.5 V VBAT_RF -0.2 4.5 V USB_VBUS 1.19 2.0 V Voltage at Digital Pins -0.3 2.0 V 6.2. Power Supply Ratings Table 31: Power Supply Ratings Parameter Description Conditions Min. Typ.
LPWA Module Series 6.3. Operating and Storage Temperatures Table 32: Operating and Storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range 1) -35 + 25 + 75 ºC Extended Temperature Range 2) -40 + 85 ºC Storage Temperature Range -40 + 90 °C NOTES 1. 2. Within the operating temperature range, the module meets 3GPP specifications.
LPWA Module Series Idle State (USB/UART disconnected) LTE Cat M1 data transfer (GNSS OFF) LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s TBD - mA LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s TBD - mA LTE Cat M1 DRX = 1.28 s TBD - mA LTE Cat NB1 DRX = 1.28 s TBD - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s TBD - mA LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s TBD - mA LTE HD-FDD B1 @ 22.8 dBm TBD - mA LTE HD-FDD B2 @ 23.
LPWA Module Series LTE Cat NB1 data transfer (GNSS OFF) LTE HD-FDD B66 @ 23.19 dBm TBD - mA LTE HD-FDD B1 @ 22.7 dBm TBD - mA LTE HD-FDD B2 @ 22.72 dBm TBD - mA LTE HD-FDD B3 @ 23.24 dBm TBD - mA LTE HD-FDD B4 @ 23.19 dBm TBD - mA LTE HD-FDD B5 @ 23.32 dBm TBD - mA LTE HD-FDD B8 @ 22.71 dBm TBD - mA LTE HD-FDD B12 @ 22.8 dBm TBD - mA LTE HD-FDD B13 @ 23.23 dBm TBD - mA LTE HD-FDD B17 @ 22.73 dBm TBD - mA LTE HD-FDD B18 @ 23.28 dBm TBD - mA LTE HD-FDD B19 @ 23.
LPWA Module Series 6.5. Tx Power Table 35: Tx Power Frequency Bands Max. Tx Power Min. Tx Power LTE HD-FDD: B1/B2/B3/B4/B5/B8/B12/B13/B17 6/B18/ B19/B20/B25/B26 7/B27 7/B28/B66 23 dBm ±2.7 dB < -39 dBm 6.6. RF Receiving Sensitivity Table 36: Conducted RF Receiving Sensitivity of BG952A-GL QuecOpen Frequency Band Cat NB18/3GPP LTE HD-FDD B1 -106.6/-102.3 -115.3/-107.5 LTE HD-FDD B2 -106.2/-100.3 -114.3/-107.5 LTE HD-FDD B3 -106.2/-99.3 -114/-107.5 LTE HD-FDD B4 -106.6/-102.3 -114/-107.
LPWA Module Series LTE HD-FDD B19 -107/-102.3 -115.3/-107.5 LTE HD-FDD B20 -106.6/-99.8 -114.6/-107.5 LTE HD-FDD B25 -106.4/-100.3 -114.3/-107.5 -107/-100.3 - LTE HD-FDD B27 9 -107.2/-100.8 - LTE HD-FDD B28 -106.6/-100.8 -114.6/-107.5 LTE HD-FDD B66 -106.8/-101.8 -114.9/-107.5 LTE HD-FDD B26 9 6.7. ESD If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent.
LPWA Module Series 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1.
LPWA Module Series 19.90±0.20 1.95 1.10 0.55 1.10 0.25 1.00 1.00 Pin 1 5.10 0.25 8.50 23.60±0.20 1.00 0.85 1.70 1.90 1.10 1.00 1.70 1.00 1.70 0.70 0.50 0.25 0.55 0.25 1.10 40x1.0 62x0.7 40x1.0 62x1.10 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard.
LPWA Module Series 7.2. Recommended Footprint 9.95 9.15 7.45 1.00 1.10 19.90±0.20 1.95 9.95 9.15 7.15 0.55 1.10 0.25 1.00 Pin 1 0.25 2.50 1.70 1.70 1.10 0.85 1.00 2.55 1.10 1.00 0.70 1.10 2.50 1.10 11.80 11.00 9.60 7.65 5.95 4.25 1.70 0.20 1.90 0.85 1.70 1.70 23.60±0.20 0.85 0.15 0.25 11.80 11.00 9.70 7.65 5.95 4.25 1.70 1.10 0.25 4.25 5.95 62x1.10 4.25 5.95 40x1.0 62x0.7 40x1.0 Figure 33: Recommended Footprint (Top View) NOTES 1. 2. 3.
LPWA Module Series 7.3. Top and Bottom Views Figure 34: Top and Bottom Views NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel.
LPWA Module Series 8 Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
LPWA Module Series NOTES 1. 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed.
LPWA Module Series Table 38: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150 °C and 200 °C) 70–120 s Reflow Zone Max slope 1–3 °C/s Reflow time (D: over 220 °C) 45–70 s Max temperature 235–246 °C Cooling down slope -1.5 to -3 °C/s Reflow Cycle Max reflow cycle 1 NOTE 1. 2. 3.
LPWA Module Series Figure 36: Carrier Tape Dimension Drawing Table 39: Carrier Tape Dimension Table (Unit: mm) W P T A0 B0 K0 K1 F E 44 32 0.35 20.2 24 3.15 6.65 20.2 1.75 8.3.2.
LPWA Module Series 330 100 44.5 8.3.3. Packing Process Place the module onto the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape on the plastic reel and use the protective tape for protection. One plastic reel can load 250 modules. Place the packaged plastic reel, humidity indicator card and desiccant bag inside a vacuum bag, then vacuumize it. Place the vacuum-packed plastic reel inside a pizza box. Place 4 pizza boxes inside 1 carton and seal it.
LPWA Module Series 9 Appendix A References Table 41: Related Documents SN Document Name [1] Quectel_BG770A-GL&BG95xA-GL_GNSS_Application_Note [2] Quectel_LTE_OPEN_EVB_User_Guide [3] Quectel_BG77xA-GL&BG95xA-GL_AT_Commands_Manual [4] Quectel_BG77xA-GL&BG95xA-GL_QCFG_AT_Commands_Manual [5] Quectel_RF_Layout_Application_Note [6] Quectel_Module_Secondary_SMT_Application_Note [7] Quectel_BG952A-GL_QuecOpen_GPIO_Configuration [8] Quectel_BG950A-GL&BG951A-GL_TE-A_User_Guide Table 42: Terms and
LPWA Module Series EGPRS Enhanced General Packet Radio Service EGSM Extended GSM (Global System for Mobile Communications) EPC Evolved Packet Core ESD Electrostatic Discharge FDD Frequency Division Duplex GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I2C Inter-Integrated Circuit LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station MSL Moisture Sensitivity Level
LPWA Module Series SPI Serial Peripheral Interface TDM Time-Division Multiplexing TVS Transient Voltage Suppressor UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VOH
LPWA Module Series CE Statement The minimum distance between the user and/or any bystander and the radiating structure of the transmitter is 20cm. Hereby, We, Quectel Wireless Solutions Co., Ltd. declares that the radio equipment type BG951A-GL is in compliance with the Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address: Building 5, Shanghai Business Park Phase III (Area B), No.
LPWA Module Series ❒ NB LTE Band2/25:≤11.000dBi ❒ NB LTE Band4/66:≤8.000dBi ❒ NB LTE Band5:≤12.541 dBi ❒ NB LTE Band12:≤11.798dBi ❒ NB LTE Band13:≤12.214dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
LPWA Module Series The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
LPWA Module Series and must not transmit simultaneously with any other antenna or transmitter. L'autre utilisé pour l'émetteur doit être installé pour fournir une distance de séparation d'au moins 20 cm de toutes les personnes et ne doit pas être colocalisé ou fonctionner conjointement avec une autre antenne ou un autre émetteur.
LPWA Module Series “Contains IC: 10224A-022BG952AGL” or “where: 10224A-022BG952AGL is the module’s certification number”. Le produit hôte doit être correctement étiqueté pour identifier les modules dans le produit hôte.
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