Datasheet

MF1S50YYX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 2 May 2011
196330 28 of 39
NXP Semiconductors
MF1S50yyX
MIFARE Classic 1K - Mainstream contactless smart card IC
14. Wafer specification
For more details on the wafer delivery forms see Ref. 9.
[1] The step size and the gap between chips may vary due to changing foil expansion
[2] Pads VSS and TESTIO are disconnected when wafer is sawn.
14.1 Fail die identification
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/visual inspection. No ink dots are applied.
Table 29. Wafer specifications MF1S50yyXDUy
Wafer
diameter 200 mm typical (8 inches)
maximum diameter after foil expansion 210 mm
thickness MF1S50yyXDUD 120 μm ± 15 μm
MF1S50yyXDUF 75 μm ± 10 μm
flatness not applicable
Potential Good Dies per Wafer (PGDW) est. 66264
Wafer backside
material Si
treatment
ground and stress relieve
roughness R
a
max = 0.5 μm
R
t
max = 5 μm
Chip dimensions
step size
[1]
x = 659 μm
y = 694 μm
gap between chips
[1]
typical = 19 μm
minimum = 5 μm
Passivation
type sandwich structure
material PSG / nitride
thickness 500 nm / 600 nm
Au bump (substrate connected to VSS)
material > 99.9 % pure Au
hardness 35 to 80 HV 0.005
shear strength > 70 MPa
height 18 μm
height uniformity within a die = ±2 μm
within a wafer = ±3 μm
wafer to wafer = ±4 μm
flatness minimum = ±1.5 μm
size LA, LB, VSS, TEST
[2]
=66 μm × 66 μm
size variation ±5 μm
under bump metallization sputtered TiW